^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sound/soc/rockchip/rockchip_i2s.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * ALSA SoC Audio Layer - Rockchip I2S Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Jianqun xu <jay.xu@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _ROCKCHIP_IIS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _ROCKCHIP_IIS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * TXCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * transmit operation control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define I2S_TXCR_RCNT_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define I2S_TXCR_CSR_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2S_TXCR_HWT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I2S_TXCR_SJM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2S_TXCR_FBM_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2S_TXCR_IBM_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2S_TXCR_PBM_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2S_TXCR_TFS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2S_TXCR_VDW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * RXCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * receive operation control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2S_RXCR_CSR_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2S_RXCR_HWT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2S_RXCR_SJM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2S_RXCR_FBM_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2S_RXCR_IBM_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2S_RXCR_PBM_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2S_RXCR_TFS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define I2S_RXCR_VDW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * CKR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * clock generation register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define I2S_CKR_TRCM_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I2S_CKR_MSS_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I2S_CKR_CKP_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I2S_CKR_CKP_NORMAL (0 << I2S_CKR_CKP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define I2S_CKR_CKP_INVERTED (1 << I2S_CKR_CKP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define I2S_CKR_RLP_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define I2S_CKR_RLP_INVERTED (1 << I2S_CKR_RLP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define I2S_CKR_RLP_MASK (1 << I2S_CKR_RLP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define I2S_CKR_TLP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define I2S_CKR_TLP_INVERTED (1 << I2S_CKR_TLP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define I2S_CKR_TLP_MASK (1 << I2S_CKR_TLP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define I2S_CKR_MDIV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define I2S_CKR_RSD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define I2S_CKR_TSD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * FIFOLR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * FIFO level register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define I2S_FIFOLR_RFL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define I2S_FIFOLR_TFL3_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define I2S_FIFOLR_TFL2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define I2S_FIFOLR_TFL1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define I2S_FIFOLR_TFL0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * DMACR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * DMA control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define I2S_DMACR_RDE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define I2S_DMACR_RDL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define I2S_DMACR_TDE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define I2S_DMACR_TDL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * INTCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * interrupt control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define I2S_INTCR_RFT_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define I2S_INTCR_RXOIC BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define I2S_INTCR_RXOIE_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define I2S_INTCR_RXFIE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define I2S_INTCR_TFT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define I2S_INTCR_TXUIC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define I2S_INTCR_TXUIE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * INTSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * interrupt status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define I2S_INTSR_TXEIE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define I2S_INTSR_RXOI_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define I2S_INTSR_RXFI_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define I2S_INTSR_TXUI_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define I2S_INTSR_TXEI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * XFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Transfer start register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define I2S_XFER_RXS_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define I2S_XFER_TXS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * CLR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * clear SCLK domain logic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define I2S_CLR_RXC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define I2S_CLR_TXC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * TXDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Transimt FIFO data register, write only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define I2S_TXDR_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * RXDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Receive FIFO data register, write only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define I2S_RXDR_MASK (0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Clock divider id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ROCKCHIP_DIV_MCLK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ROCKCHIP_DIV_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* channel select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define I2S_CSR_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define I2S_CHN_2 (0 << I2S_CSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define I2S_CHN_4 (1 << I2S_CSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define I2S_CHN_6 (2 << I2S_CSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define I2S_CHN_8 (3 << I2S_CSR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* I2S REGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define I2S_TXCR (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define I2S_RXCR (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define I2S_CKR (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define I2S_FIFOLR (0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define I2S_DMACR (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define I2S_INTCR (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define I2S_INTSR (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define I2S_XFER (0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define I2S_CLR (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define I2S_TXDR (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define I2S_RXDR (0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* io direction cfg register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define I2S_IO_DIRECTION_MASK (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define I2S_IO_8CH_OUT_2CH_IN (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define I2S_IO_6CH_OUT_4CH_IN (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define I2S_IO_4CH_OUT_6CH_IN (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define I2S_IO_2CH_OUT_8CH_IN (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #endif /* _ROCKCHIP_IIS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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