^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* sound/soc/rockchip/rockchip_i2s.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * ALSA SoC Audio Layer - Rockchip I2S Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Jianqun <jay.xu@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "rockchip_i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRV_NAME "rockchip-i2s"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct rk_i2s_pins {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct rk_i2s_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct snd_dmaengine_dai_dma_data playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bool has_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bool has_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Used to indicate the tx/rx status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * I2S controller hopes to start the tx and rx together,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * also to stop them when they are both try to stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool tx_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bool rx_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bool is_master_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct rk_i2s_pins *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int bclk_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) spinlock_t lock; /* tx/rx lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int clk_trcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int i2s_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) regcache_cache_only(i2s->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clk_disable_unprepare(i2s->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int i2s_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = clk_prepare_enable(i2s->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dev_err(i2s->dev, "clock enable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) regcache_cache_only(i2s->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) regcache_mark_dirty(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = regcache_sync(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clk_disable_unprepare(i2s->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int retry = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) spin_lock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) regmap_update_bits(i2s->regmap, I2S_DMACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) regmap_update_bits(i2s->regmap, I2S_XFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) I2S_XFER_TXS_START | I2S_XFER_RXS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) I2S_XFER_TXS_START | I2S_XFER_RXS_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) i2s->tx_start = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) i2s->tx_start = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regmap_update_bits(i2s->regmap, I2S_DMACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!i2s->rx_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regmap_update_bits(i2s->regmap, I2S_XFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) I2S_XFER_TXS_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) I2S_XFER_RXS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) I2S_XFER_TXS_STOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) I2S_XFER_RXS_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regmap_update_bits(i2s->regmap, I2S_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) I2S_CLR_TXC | I2S_CLR_RXC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) I2S_CLR_TXC | I2S_CLR_RXC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) regmap_read(i2s->regmap, I2S_CLR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Should wait for clear operation to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) while (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) regmap_read(i2s->regmap, I2S_CLR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) retry--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (!retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_warn(i2s->dev, "fail to clear\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spin_unlock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int retry = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) spin_lock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) regmap_update_bits(i2s->regmap, I2S_DMACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) regmap_update_bits(i2s->regmap, I2S_XFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) I2S_XFER_TXS_START | I2S_XFER_RXS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) I2S_XFER_TXS_START | I2S_XFER_RXS_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) i2s->rx_start = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) i2s->rx_start = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_update_bits(i2s->regmap, I2S_DMACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!i2s->tx_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) regmap_update_bits(i2s->regmap, I2S_XFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) I2S_XFER_TXS_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) I2S_XFER_RXS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) I2S_XFER_TXS_STOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) I2S_XFER_RXS_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) regmap_update_bits(i2s->regmap, I2S_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) I2S_CLR_TXC | I2S_CLR_RXC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) I2S_CLR_TXC | I2S_CLR_RXC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) regmap_read(i2s->regmap, I2S_CLR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Should wait for clear operation to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) while (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) regmap_read(i2s->regmap, I2S_CLR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) retry--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_warn(i2s->dev, "fail to clear\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) spin_unlock(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct rk_i2s_dev *i2s = to_info(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int mask = 0, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pm_runtime_get_sync(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mask = I2S_CKR_MSS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Set source clock in Master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) val = I2S_CKR_MSS_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) i2s->is_master_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val = I2S_CKR_MSS_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) i2s->is_master_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto err_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) val = I2S_CKR_CKP_NORMAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) I2S_CKR_TLP_NORMAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) I2S_CKR_RLP_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val = I2S_CKR_CKP_NORMAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) I2S_CKR_TLP_INVERTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) I2S_CKR_RLP_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val = I2S_CKR_CKP_INVERTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) I2S_CKR_TLP_NORMAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) I2S_CKR_RLP_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val = I2S_CKR_CKP_INVERTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) I2S_CKR_TLP_INVERTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) I2S_CKR_RLP_INVERTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) goto err_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) val = I2S_TXCR_IBM_RSJM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val = I2S_TXCR_IBM_LSJM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val = I2S_TXCR_IBM_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) val = I2S_TXCR_TFS_PCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto err_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) val = I2S_RXCR_IBM_RSJM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) val = I2S_RXCR_IBM_LSJM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val = I2S_RXCR_IBM_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val = I2S_RXCR_TFS_PCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) goto err_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) err_pm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pm_runtime_put(cpu_dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct rk_i2s_dev *i2s = to_info(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (i2s->is_master_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mclk_rate = clk_get_rate(i2s->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) bclk_rate = i2s->bclk_ratio * params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!bclk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) div_lrck = bclk_rate / params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) regmap_update_bits(i2s->regmap, I2S_CKR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) I2S_CKR_MDIV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) I2S_CKR_MDIV(div_bclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) regmap_update_bits(i2s->regmap, I2S_CKR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) I2S_CKR_TSD_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) I2S_CKR_RSD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) I2S_CKR_TSD(div_lrck) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) I2S_CKR_RSD(div_lrck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) val |= I2S_TXCR_VDW(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) val |= I2S_TXCR_VDW(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case SNDRV_PCM_FORMAT_S20_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) val |= I2S_TXCR_VDW(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val |= I2S_TXCR_VDW(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) val |= I2S_TXCR_VDW(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) switch (params_channels(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val |= I2S_CHN_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) val |= I2S_CHN_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) val |= I2S_CHN_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val |= I2S_CHN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(i2s->dev, "invalid channel: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) params_channels(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) regmap_update_bits(i2s->regmap, I2S_RXCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) regmap_update_bits(i2s->regmap, I2S_TXCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!IS_ERR(i2s->grf) && i2s->pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) regmap_read(i2s->regmap, I2S_TXCR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) val &= I2S_TXCR_CSR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case I2S_CHN_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) val = I2S_IO_4CH_OUT_6CH_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case I2S_CHN_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) val = I2S_IO_6CH_OUT_4CH_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case I2S_CHN_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) val = I2S_IO_8CH_OUT_2CH_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) val = I2S_IO_2CH_OUT_8CH_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) val <<= i2s->pins->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) regmap_write(i2s->grf, i2s->pins->reg_offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) I2S_DMACR_TDL(16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) I2S_DMACR_RDL(16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct rk_i2s_dev *i2s = to_info(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) rockchip_snd_rxctrl(i2s, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) rockchip_snd_txctrl(i2s, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) rockchip_snd_rxctrl(i2s, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rockchip_snd_txctrl(i2s, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct rk_i2s_dev *i2s = to_info(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) i2s->bclk_ratio = ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct rk_i2s_dev *i2s = to_info(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (freq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = clk_set_rate(i2s->mclk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) snd_soc_dai_init_dma_data(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) i2s->has_playback ? &i2s->playback_dma_data : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) i2s->has_capture ? &i2s->capture_dma_data : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .hw_params = rockchip_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .set_sysclk = rockchip_i2s_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .set_fmt = rockchip_i2s_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .trigger = rockchip_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct snd_soc_dai_driver rockchip_i2s_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .probe = rockchip_i2s_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .ops = &rockchip_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const struct snd_soc_component_driver rockchip_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case I2S_TXCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case I2S_RXCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case I2S_CKR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case I2S_DMACR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case I2S_INTCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case I2S_XFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case I2S_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case I2S_TXDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case I2S_TXCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case I2S_RXCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case I2S_CKR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case I2S_DMACR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case I2S_INTCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case I2S_XFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case I2S_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case I2S_TXDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case I2S_RXDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case I2S_FIFOLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case I2S_INTSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case I2S_INTSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case I2S_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case I2S_FIFOLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case I2S_TXDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case I2S_RXDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case I2S_RXDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct reg_default rockchip_i2s_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x00, 0x0000000f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x04, 0x0000000f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x08, 0x00071f1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x10, 0x001f0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x14, 0x01f00000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct regmap_config rockchip_i2s_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .max_register = I2S_RXDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .reg_defaults = rockchip_i2s_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .writeable_reg = rockchip_i2s_wr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .readable_reg = rockchip_i2s_rd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .volatile_reg = rockchip_i2s_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .precious_reg = rockchip_i2s_precious_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const struct rk_i2s_pins rk3399_i2s_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .reg_offset = 0xe220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #ifdef CONFIG_CPU_PX30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { .compatible = "rockchip,px30-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #ifdef CONFIG_CPU_RK1808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { .compatible = "rockchip,rk1808-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #ifdef CONFIG_CPU_RK3036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { .compatible = "rockchip,rk3036-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { .compatible = "rockchip,rk3066-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #ifdef CONFIG_CPU_RK312X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { .compatible = "rockchip,rk3128-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #ifdef CONFIG_CPU_RK3188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { .compatible = "rockchip,rk3188-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef CONFIG_CPU_RK322X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { .compatible = "rockchip,rk3228-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #ifdef CONFIG_CPU_RK3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { .compatible = "rockchip,rk3288-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #ifdef CONFIG_CPU_RK3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { .compatible = "rockchip,rk3308-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #ifdef CONFIG_CPU_RK3328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { .compatible = "rockchip,rk3328-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #ifdef CONFIG_CPU_RK3366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { .compatible = "rockchip,rk3366-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #ifdef CONFIG_CPU_RK3368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { .compatible = "rockchip,rk3368-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #ifdef CONFIG_CPU_RK3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #ifdef CONFIG_CPU_RV1126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { .compatible = "rockchip,rv1126-i2s", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct snd_soc_dai_driver **dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct device_node *node = i2s->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct snd_soc_dai_driver *dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct property *dma_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) const char *dma_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (!strcmp(dma_name, "tx"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) i2s->has_playback = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!strcmp(dma_name, "rx"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) i2s->has_capture = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) sizeof(*dai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (!dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (i2s->has_playback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dai->playback.stream_name = "Playback";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dai->playback.channels_min = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dai->playback.channels_max = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SNDRV_PCM_FMTBIT_S20_3LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SNDRV_PCM_FMTBIT_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) i2s->playback_dma_data.addr = res->start + I2S_TXDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) i2s->playback_dma_data.maxburst = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (val >= 2 && val <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dai->playback.channels_max = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (i2s->has_capture) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dai->capture.stream_name = "Capture";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dai->capture.channels_min = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dai->capture.channels_max = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) SNDRV_PCM_FMTBIT_S20_3LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) SNDRV_PCM_FMTBIT_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) i2s->capture_dma_data.addr = res->start + I2S_RXDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) i2s->capture_dma_data.maxburst = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (val >= 2 && val <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dai->capture.channels_max = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) i2s->clk_trcm = I2S_CKR_TRCM_TXRX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (!of_property_read_u32(node, "rockchip,clk-trcm", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (val >= 0 && val <= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) i2s->clk_trcm = val << I2S_CKR_TRCM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (i2s->clk_trcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dai->symmetric_rates = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) regmap_update_bits(i2s->regmap, I2S_CKR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) I2S_CKR_TRCM_MASK, i2s->clk_trcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) *dp = dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int rockchip_i2s_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct rk_i2s_dev *i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct snd_soc_dai_driver *dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!i2s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spin_lock_init(&i2s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) i2s->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (!IS_ERR(i2s->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (!of_id || !of_id->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) i2s->pins = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) &rockchip_i2s_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (IS_ERR(i2s->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "Failed to initialise managed register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return PTR_ERR(i2s->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) i2s->bclk_ratio = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_set_drvdata(&pdev->dev, i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (IS_ERR(i2s->mclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return PTR_ERR(i2s->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* try to prepare related clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (IS_ERR(i2s->hclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return PTR_ERR(i2s->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = clk_prepare_enable(i2s->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_err(i2s->dev, "hclock enable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = i2s_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = rockchip_i2s_init_dai(i2s, res, &dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) &rockchip_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_err(&pdev->dev, "Could not register DAI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (of_property_read_bool(node, "rockchip,no-dmaengine"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(&pdev->dev, "Could not register PCM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) goto err_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) err_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) i2s_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) clk_disable_unprepare(i2s->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int rockchip_i2s_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) i2s_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) clk_disable_unprepare(i2s->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const struct dev_pm_ops rockchip_i2s_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static struct platform_driver rockchip_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .probe = rockchip_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .remove = rockchip_i2s_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .of_match_table = of_match_ptr(rockchip_i2s_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .pm = &rockchip_i2s_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) module_platform_driver(rockchip_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) MODULE_ALIAS("platform:" DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags