^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef __Q6AFE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define __Q6AFE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <dt-bindings/sound/qcom,q6afe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define AFE_PORT_MAX 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MSM_AFE_PORT_TYPE_RX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MSM_AFE_PORT_TYPE_TX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AFE_MAX_PORTS AFE_PORT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define Q6AFE_MAX_MI2S_LINES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AFE_MAX_CHAN_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPAIF_DIG_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPAIF_BIT_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LPAIF_OSR_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Clock ID for Primary I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Clock ID for Primary I2S EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Clock ID for Secondary I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Clock ID for Secondary I2S EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Clock ID for Tertiary I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Clock ID for Tertiary I2S EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Clock ID for Quartnery I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Clock ID for Quartnery I2S EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Clock ID for Speaker I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Clock ID for Speaker I2S EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Clock ID for Speaker I2S OSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Clock ID for QUINARY I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Clock ID for QUINARY I2S EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Clock ID for SENARY I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Clock ID for SENARY I2S EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Clock ID for INT0 I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Clock ID for INT1 I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Clock ID for INT2 I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Clock ID for INT3 I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Clock ID for INT4 I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Clock ID for INT5 I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Clock ID for INT6 I2S IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Clock ID for QUINARY MI2S OSR CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Clock ID for Primary PCM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Clock ID for Primary PCM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Clock ID for Secondary PCM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Clock ID for Secondary PCM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Clock ID for Tertiary PCM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Clock ID for Tertiary PCM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Clock ID for Quartery PCM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Clock ID for Quartery PCM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Clock ID for Quinary PCM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Clock ID for Quinary PCM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Clock ID for QUINARY PCM OSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /** Clock ID for Primary TDM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /** Clock ID for Primary TDM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /** Clock ID for Secondary TDM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /** Clock ID for Secondary TDM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /** Clock ID for Tertiary TDM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /** Clock ID for Tertiary TDM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /** Clock ID for Quartery TDM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /** Clock ID for Quartery TDM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /** Clock ID for Quinary TDM IBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /** Clock ID for Quinary TDM EBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /** Clock ID for Quinary TDM OSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Clock ID for MCLK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Clock ID for MCLK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Clock ID for MCLK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Clock ID for MCLK4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Clock ID for Internal Digital Codec Core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Clock ID for INT MCLK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Clock ID for INT MCLK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Clock attribute for invalid use (reserved for internal usage) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Clock attribute for no couple case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Clock attribute for dividend couple case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Clock attribute for divisor couple case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Clock attribute for invert and no couple case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define Q6AFE_CMAP_INVALID 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct q6afe_hdmi_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u16 datatype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u16 channel_allocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u16 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct q6afe_slim_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u16 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u16 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 ch_mapping[AFE_MAX_CHAN_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct q6afe_i2s_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u16 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u16 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 sd_line_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct q6afe_tdm_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u16 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u16 data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u16 sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u16 sync_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u16 nslots_per_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u16 slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u16 slot_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 data_align_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u16 ch_mapping[AFE_MAX_CHAN_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct q6afe_cdc_dma_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u16 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u16 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u16 data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u16 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 active_channels_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct q6afe_port_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct q6afe_hdmi_cfg hdmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct q6afe_slim_cfg slim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct q6afe_i2s_cfg i2s_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct q6afe_tdm_cfg tdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct q6afe_cdc_dma_cfg dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct q6afe_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int q6afe_port_start(struct q6afe_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int q6afe_port_stop(struct q6afe_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void q6afe_port_put(struct q6afe_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int q6afe_get_port_id(int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void q6afe_hdmi_port_prepare(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct q6afe_hdmi_cfg *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void q6afe_slim_port_prepare(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct q6afe_slim_cfg *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct q6afe_cdc_dma_cfg *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int clk_src, int clk_root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int freq, int dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int q6afe_set_lpass_clock(struct device *dev, int clk_id, int clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int clk_root, unsigned int freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) char *client_name, uint32_t *client_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) uint32_t client_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif /* __Q6AFE_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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