^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2018, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kref.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/soc/qcom/apr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "q6dsp-errno.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "q6core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "q6afe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* AFE CMDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AFE_PORT_CMD_DEVICE_START 0x000100E5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AFE_PORT_CMD_DEVICE_STOP 0x000100E6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AFE_SVC_CMD_SET_PARAM 0x000100f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AFE_PARAM_ID_HDMI_CONFIG 0x00010210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AFE_MODULE_TDM 0x0001028A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG 0x00010239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AFE_PARAM_ID_I2S_CONFIG 0x0001020D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AFE_PARAM_ID_TDM_CONFIG 0x0001029D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AFE_PARAM_ID_CODEC_DMA_CONFIG 0x000102B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST 0x000100f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* I2S config specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AFE_API_VERSION_I2S_CONFIG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AFE_PORT_I2S_SD0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AFE_PORT_I2S_SD1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AFE_PORT_I2S_SD2 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AFE_PORT_I2S_SD3 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AFE_PORT_I2S_SD0_MASK BIT(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AFE_PORT_I2S_SD1_MASK BIT(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AFE_PORT_I2S_SD2_MASK BIT(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AFE_PORT_I2S_SD3_MASK BIT(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AFE_PORT_I2S_QUAD01 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AFE_PORT_I2S_QUAD23 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AFE_PORT_I2S_6CHS 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AFE_PORT_I2S_8CHS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AFE_PORT_I2S_MONO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AFE_PORT_I2S_STEREO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AFE_LINEAR_PCM_DATA 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Port IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AFE_API_VERSION_HDMI_CONFIG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AFE_PORT_ID_HDMI_OVER_DP_RX 0x6020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AFE_API_VERSION_SLIMBUS_CONFIG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Clock set API version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AFE_API_VERSION_CLOCK_SET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define Q6AFE_LPASS_CLK_CONFIG_API_VERSION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AFE_MODULE_CLOCK_SET 0x0001028F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AFE_PARAM_ID_CLOCK_SET 0x00010290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* SLIMbus Rx port on channel 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* SLIMbus Tx port on channel 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* SLIMbus Rx port on channel 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* SLIMbus Tx port on channel 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* SLIMbus Rx port on channel 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* SLIMbus Tx port on channel 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* SLIMbus Rx port on channel 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* SLIMbus Tx port on channel 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* SLIMbus Rx port on channel 4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* SLIMbus Tx port on channel 4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* SLIMbus Rx port on channel 5. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* SLIMbus Tx port on channel 5. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* SLIMbus Rx port on channel 6. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* SLIMbus Tx port on channel 6. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Start of the range of port IDs for TDM devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* End of the range of port IDs for TDM devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AFE_PORT_ID_TDM_PORT_RANGE_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) (AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Size of the range of port IDs for TDM ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (AFE_PORT_ID_TDM_PORT_RANGE_END - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) AFE_PORT_ID_TDM_PORT_RANGE_START+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AFE_PORT_ID_PRIMARY_TDM_RX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AFE_PORT_ID_PRIMARY_TDM_RX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (AFE_PORT_ID_PRIMARY_TDM_RX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AFE_PORT_ID_PRIMARY_TDM_RX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (AFE_PORT_ID_PRIMARY_TDM_RX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AFE_PORT_ID_PRIMARY_TDM_RX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (AFE_PORT_ID_PRIMARY_TDM_RX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AFE_PORT_ID_PRIMARY_TDM_RX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (AFE_PORT_ID_PRIMARY_TDM_RX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AFE_PORT_ID_PRIMARY_TDM_RX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AFE_PORT_ID_PRIMARY_TDM_RX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AFE_PORT_ID_PRIMARY_TDM_RX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AFE_PORT_ID_PRIMARY_TDM_TX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AFE_PORT_ID_PRIMARY_TDM_TX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (AFE_PORT_ID_PRIMARY_TDM_TX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AFE_PORT_ID_PRIMARY_TDM_TX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (AFE_PORT_ID_PRIMARY_TDM_TX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AFE_PORT_ID_PRIMARY_TDM_TX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) (AFE_PORT_ID_PRIMARY_TDM_TX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AFE_PORT_ID_PRIMARY_TDM_TX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (AFE_PORT_ID_PRIMARY_TDM_TX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AFE_PORT_ID_PRIMARY_TDM_TX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AFE_PORT_ID_PRIMARY_TDM_TX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AFE_PORT_ID_PRIMARY_TDM_TX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AFE_PORT_ID_SECONDARY_TDM_RX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AFE_PORT_ID_SECONDARY_TDM_RX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (AFE_PORT_ID_SECONDARY_TDM_RX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AFE_PORT_ID_SECONDARY_TDM_RX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (AFE_PORT_ID_SECONDARY_TDM_RX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AFE_PORT_ID_SECONDARY_TDM_RX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) (AFE_PORT_ID_SECONDARY_TDM_RX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AFE_PORT_ID_SECONDARY_TDM_RX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) (AFE_PORT_ID_SECONDARY_TDM_RX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AFE_PORT_ID_SECONDARY_TDM_RX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AFE_PORT_ID_SECONDARY_TDM_RX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AFE_PORT_ID_SECONDARY_TDM_RX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AFE_PORT_ID_SECONDARY_TDM_TX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AFE_PORT_ID_SECONDARY_TDM_TX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (AFE_PORT_ID_SECONDARY_TDM_TX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AFE_PORT_ID_SECONDARY_TDM_TX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) (AFE_PORT_ID_SECONDARY_TDM_TX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AFE_PORT_ID_SECONDARY_TDM_TX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (AFE_PORT_ID_SECONDARY_TDM_TX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AFE_PORT_ID_SECONDARY_TDM_TX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) (AFE_PORT_ID_SECONDARY_TDM_TX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AFE_PORT_ID_SECONDARY_TDM_TX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AFE_PORT_ID_SECONDARY_TDM_TX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AFE_PORT_ID_SECONDARY_TDM_TX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AFE_PORT_ID_TERTIARY_TDM_RX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AFE_PORT_ID_TERTIARY_TDM_RX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) (AFE_PORT_ID_TERTIARY_TDM_RX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AFE_PORT_ID_TERTIARY_TDM_RX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) (AFE_PORT_ID_TERTIARY_TDM_RX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AFE_PORT_ID_TERTIARY_TDM_RX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (AFE_PORT_ID_TERTIARY_TDM_RX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AFE_PORT_ID_TERTIARY_TDM_RX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (AFE_PORT_ID_TERTIARY_TDM_RX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AFE_PORT_ID_TERTIARY_TDM_RX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AFE_PORT_ID_TERTIARY_TDM_RX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AFE_PORT_ID_TERTIARY_TDM_RX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AFE_PORT_ID_TERTIARY_TDM_TX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AFE_PORT_ID_TERTIARY_TDM_TX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (AFE_PORT_ID_TERTIARY_TDM_TX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AFE_PORT_ID_TERTIARY_TDM_TX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (AFE_PORT_ID_TERTIARY_TDM_TX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AFE_PORT_ID_TERTIARY_TDM_TX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) (AFE_PORT_ID_TERTIARY_TDM_TX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AFE_PORT_ID_TERTIARY_TDM_TX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) (AFE_PORT_ID_TERTIARY_TDM_TX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AFE_PORT_ID_TERTIARY_TDM_TX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AFE_PORT_ID_TERTIARY_TDM_TX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AFE_PORT_ID_TERTIARY_TDM_TX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AFE_PORT_ID_QUATERNARY_TDM_RX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AFE_PORT_ID_QUATERNARY_TDM_TX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AFE_PORT_ID_QUINARY_TDM_RX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define AFE_PORT_ID_QUINARY_TDM_RX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) (AFE_PORT_ID_QUINARY_TDM_RX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define AFE_PORT_ID_QUINARY_TDM_RX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (AFE_PORT_ID_QUINARY_TDM_RX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define AFE_PORT_ID_QUINARY_TDM_RX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (AFE_PORT_ID_QUINARY_TDM_RX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define AFE_PORT_ID_QUINARY_TDM_RX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (AFE_PORT_ID_QUINARY_TDM_RX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AFE_PORT_ID_QUINARY_TDM_RX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (AFE_PORT_ID_QUINARY_TDM_RX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define AFE_PORT_ID_QUINARY_TDM_RX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) (AFE_PORT_ID_QUINARY_TDM_RX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define AFE_PORT_ID_QUINARY_TDM_RX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) (AFE_PORT_ID_QUINARY_TDM_RX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define AFE_PORT_ID_QUINARY_TDM_TX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define AFE_PORT_ID_QUINARY_TDM_TX_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (AFE_PORT_ID_QUINARY_TDM_TX + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define AFE_PORT_ID_QUINARY_TDM_TX_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (AFE_PORT_ID_QUINARY_TDM_TX + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define AFE_PORT_ID_QUINARY_TDM_TX_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) (AFE_PORT_ID_QUINARY_TDM_TX + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define AFE_PORT_ID_QUINARY_TDM_TX_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (AFE_PORT_ID_QUINARY_TDM_TX + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define AFE_PORT_ID_QUINARY_TDM_TX_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (AFE_PORT_ID_QUINARY_TDM_TX + 0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define AFE_PORT_ID_QUINARY_TDM_TX_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) (AFE_PORT_ID_QUINARY_TDM_TX + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define AFE_PORT_ID_QUINARY_TDM_TX_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) (AFE_PORT_ID_QUINARY_TDM_TX + 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* AFE WSA Codec DMA Rx port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 0xB000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* AFE WSA Codec DMA Tx port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 0xB001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* AFE WSA Codec DMA Rx port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 0xB002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* AFE WSA Codec DMA Tx port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 0xB003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* AFE WSA Codec DMA Tx port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 0xB005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* AFE VA Codec DMA Tx port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define AFE_PORT_ID_VA_CODEC_DMA_TX_0 0xB021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* AFE VA Codec DMA Tx port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define AFE_PORT_ID_VA_CODEC_DMA_TX_1 0xB023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* AFE VA Codec DMA Tx port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define AFE_PORT_ID_VA_CODEC_DMA_TX_2 0xB025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* AFE Rx Codec DMA Rx port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define AFE_PORT_ID_RX_CODEC_DMA_RX_0 0xB030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* AFE Tx Codec DMA Tx port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define AFE_PORT_ID_TX_CODEC_DMA_TX_0 0xB031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* AFE Rx Codec DMA Rx port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define AFE_PORT_ID_RX_CODEC_DMA_RX_1 0xB032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* AFE Tx Codec DMA Tx port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define AFE_PORT_ID_TX_CODEC_DMA_TX_1 0xB033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* AFE Rx Codec DMA Rx port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define AFE_PORT_ID_RX_CODEC_DMA_RX_2 0xB034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* AFE Tx Codec DMA Tx port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define AFE_PORT_ID_TX_CODEC_DMA_TX_2 0xB035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* AFE Rx Codec DMA Rx port 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define AFE_PORT_ID_RX_CODEC_DMA_RX_3 0xB036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* AFE Tx Codec DMA Tx port 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define AFE_PORT_ID_TX_CODEC_DMA_TX_3 0xB037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* AFE Rx Codec DMA Rx port 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define AFE_PORT_ID_RX_CODEC_DMA_RX_4 0xB038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* AFE Tx Codec DMA Tx port 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define AFE_PORT_ID_TX_CODEC_DMA_TX_4 0xB039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* AFE Rx Codec DMA Rx port 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define AFE_PORT_ID_RX_CODEC_DMA_RX_5 0xB03A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* AFE Tx Codec DMA Tx port 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define AFE_PORT_ID_TX_CODEC_DMA_TX_5 0xB03B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* AFE Rx Codec DMA Rx port 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define AFE_PORT_ID_RX_CODEC_DMA_RX_6 0xB03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* AFE Rx Codec DMA Rx port 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define AFE_PORT_ID_RX_CODEC_DMA_RX_7 0xB03E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define Q6AFE_LPASS_MODE_CLK1_VALID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define Q6AFE_LPASS_MODE_CLK2_VALID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define AFE_API_VERSION_TDM_CONFIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define AFE_API_VERSION_CODEC_DMA_CONFIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TIMEOUT_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define AFE_CMD_RESP_AVAIL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define AFE_CMD_RESP_NONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define AFE_CLK_TOKEN 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct q6afe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct apr_device *apr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct q6core_svc_api_info ainfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct aprv2_ibasic_rsp_result_t result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct list_head port_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spinlock_t port_list_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct afe_port_cmd_device_start {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u16 port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct afe_port_cmd_device_stop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u16 port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Reserved for 32-bit alignment. This field must be set to 0.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct afe_port_param_data_v2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 param_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u16 param_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct afe_svc_cmd_set_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) uint32_t payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) uint32_t payload_address_lsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uint32_t payload_address_msw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) uint32_t mem_map_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct afe_port_cmd_set_param_v2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u16 port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u16 payload_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 payload_address_lsw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 payload_address_msw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 mem_map_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct afe_param_id_hdmi_multi_chan_audio_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 hdmi_cfg_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u16 datatype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u16 channel_allocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u16 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct afe_param_id_slimbus_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 sb_cfg_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Minor version used for tracking the version of the SLIMBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * configuration interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u16 slimbus_dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* SLIMbus hardware device ID, which is required to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * multiple SLIMbus hardware blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u16 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Bit width of the sample.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Supported values: 16, 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u16 data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Data format supported by the SLIMbus hardware. The default is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * hardware does not perform any format conversions before the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u16 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Number of channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Mapping of shared channel IDs (128 to 255) to which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * master port is to be connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Shared_channel_mapping[i] represents the shared channel assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * for audio channel i in multichannel audio data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Sampling rate of the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Supported values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * - #AFE_PORT_SAMPLE_RATE_8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * - #AFE_PORT_SAMPLE_RATE_16K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * - #AFE_PORT_SAMPLE_RATE_48K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * - #AFE_PORT_SAMPLE_RATE_96K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * - #AFE_PORT_SAMPLE_RATE_192K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct afe_clk_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 i2s_cfg_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u32 clk_val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 clk_val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u16 clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u16 clk_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u16 clk_set_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct afe_digital_clk_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 i2s_cfg_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 clk_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u16 clk_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct afe_param_id_i2s_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 i2s_cfg_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u16 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u16 channel_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u16 mono_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u16 ws_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u16 data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct afe_param_id_tdm_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 tdm_cfg_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u16 data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u16 sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u16 sync_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u16 nslots_per_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u16 ctrl_data_out_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u16 ctrl_invert_sync_pulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u16 ctrl_sync_data_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u16 slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 slot_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct afe_param_id_cdc_dma_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 cdc_dma_cfg_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u16 bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u16 data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u16 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u16 active_channels_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) union afe_port_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct afe_param_id_slimbus_cfg slim_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct afe_param_id_i2s_cfg i2s_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct afe_param_id_tdm_cfg tdm_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct afe_param_id_cdc_dma_cfg dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct afe_clk_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) uint32_t clk_set_minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) uint32_t clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) uint32_t clk_freq_in_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) uint16_t clk_attri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) uint16_t clk_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) uint32_t enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct afe_param_id_slot_mapping_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u16 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u16 bitwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 data_align_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct q6afe_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) union afe_port_config port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct afe_param_id_slot_mapping_cfg *scfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct aprv2_ibasic_rsp_result_t result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int cfg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct q6afe *afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct kref refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct afe_cmd_remote_lpass_core_hw_vote_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) uint32_t hw_block_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) char client_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct afe_cmd_remote_lpass_core_hw_devote_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) uint32_t hw_block_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uint32_t client_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct afe_port_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int is_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int is_dig_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Mapping between Virtual Port IDs to DSP AFE Port ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * On B Family SoCs DSP Port IDs are consistent across multiple SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * on A Family SoCs DSP port IDs are same as virtual Port IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static struct afe_port_map port_maps[AFE_PORT_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) [HDMI_RX] = { AFE_PORT_ID_MULTICHAN_HDMI_RX, HDMI_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) [SLIMBUS_0_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) SLIMBUS_0_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) [SLIMBUS_1_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) SLIMBUS_1_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) [SLIMBUS_2_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) SLIMBUS_2_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) [SLIMBUS_3_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) SLIMBUS_3_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) [SLIMBUS_4_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) SLIMBUS_4_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) [SLIMBUS_5_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SLIMBUS_5_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) [SLIMBUS_6_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) SLIMBUS_6_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) [SLIMBUS_0_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) SLIMBUS_0_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) [SLIMBUS_1_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) SLIMBUS_1_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) [SLIMBUS_2_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) SLIMBUS_2_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) [SLIMBUS_3_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) SLIMBUS_3_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) [SLIMBUS_4_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) SLIMBUS_4_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) [SLIMBUS_5_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SLIMBUS_5_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) [SLIMBUS_6_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) SLIMBUS_6_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) [PRIMARY_MI2S_RX] = { AFE_PORT_ID_PRIMARY_MI2S_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PRIMARY_MI2S_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) [PRIMARY_MI2S_TX] = { AFE_PORT_ID_PRIMARY_MI2S_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PRIMARY_MI2S_RX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) [SECONDARY_MI2S_RX] = { AFE_PORT_ID_SECONDARY_MI2S_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) SECONDARY_MI2S_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) [SECONDARY_MI2S_TX] = { AFE_PORT_ID_SECONDARY_MI2S_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SECONDARY_MI2S_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) [TERTIARY_MI2S_RX] = { AFE_PORT_ID_TERTIARY_MI2S_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) TERTIARY_MI2S_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) [TERTIARY_MI2S_TX] = { AFE_PORT_ID_TERTIARY_MI2S_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) TERTIARY_MI2S_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) [QUATERNARY_MI2S_RX] = { AFE_PORT_ID_QUATERNARY_MI2S_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) QUATERNARY_MI2S_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) [QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) QUATERNARY_MI2S_TX, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) [PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PRIMARY_TDM_RX_0, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) [PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PRIMARY_TDM_TX_0, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) [PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PRIMARY_TDM_RX_1, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) [PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PRIMARY_TDM_TX_1, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) [PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PRIMARY_TDM_RX_2, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PRIMARY_TDM_TX_2, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) [PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PRIMARY_TDM_RX_3, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) [PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PRIMARY_TDM_TX_3, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) [PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PRIMARY_TDM_RX_4, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) [PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PRIMARY_TDM_TX_4, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) [PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PRIMARY_TDM_RX_5, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) [PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PRIMARY_TDM_TX_5, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PRIMARY_TDM_RX_6, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) [PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PRIMARY_TDM_TX_6, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) [PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PRIMARY_TDM_RX_7, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) [PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PRIMARY_TDM_TX_7, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) [SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SECONDARY_TDM_RX_0, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) [SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SECONDARY_TDM_TX_0, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SECONDARY_TDM_RX_1, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SECONDARY_TDM_TX_1, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) [SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SECONDARY_TDM_RX_2, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) SECONDARY_TDM_TX_2, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) [SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) SECONDARY_TDM_RX_3, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) SECONDARY_TDM_TX_3, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) SECONDARY_TDM_RX_4, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) [SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) SECONDARY_TDM_TX_4, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) [SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) SECONDARY_TDM_RX_5, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) [SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) SECONDARY_TDM_TX_5, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) [SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) SECONDARY_TDM_RX_6, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) [SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) SECONDARY_TDM_TX_6, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) [SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) SECONDARY_TDM_RX_7, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) [SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) SECONDARY_TDM_TX_7, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) TERTIARY_TDM_RX_0, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) [TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) TERTIARY_TDM_TX_0, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) TERTIARY_TDM_RX_1, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) TERTIARY_TDM_TX_1, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) TERTIARY_TDM_RX_2, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) TERTIARY_TDM_TX_2, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) TERTIARY_TDM_RX_3, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) TERTIARY_TDM_TX_3, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) TERTIARY_TDM_RX_4, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) TERTIARY_TDM_TX_4, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) TERTIARY_TDM_RX_5, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) TERTIARY_TDM_TX_5, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) TERTIARY_TDM_RX_6, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) [TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) TERTIARY_TDM_TX_6, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) TERTIARY_TDM_RX_7, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) [TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) TERTIARY_TDM_TX_7, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) QUATERNARY_TDM_RX_0, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) QUATERNARY_TDM_TX_0, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) QUATERNARY_TDM_RX_1, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) QUATERNARY_TDM_TX_1, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) QUATERNARY_TDM_RX_2, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) [QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) QUATERNARY_TDM_TX_2, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) [QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) QUATERNARY_TDM_RX_3, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) QUATERNARY_TDM_TX_3, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) [QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) QUATERNARY_TDM_RX_4, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) QUATERNARY_TDM_TX_4, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) [QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) QUATERNARY_TDM_RX_5, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) QUATERNARY_TDM_TX_5, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) QUATERNARY_TDM_RX_6, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) QUATERNARY_TDM_TX_6, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) QUATERNARY_TDM_RX_7, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) QUATERNARY_TDM_TX_7, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) QUINARY_TDM_RX_0, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) QUINARY_TDM_TX_0, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) QUINARY_TDM_RX_1, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) QUINARY_TDM_TX_1, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) QUINARY_TDM_RX_2, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) QUINARY_TDM_TX_2, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) QUINARY_TDM_RX_3, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) QUINARY_TDM_TX_3, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) QUINARY_TDM_RX_4, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) QUINARY_TDM_TX_4, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) QUINARY_TDM_RX_5, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) QUINARY_TDM_TX_5, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) QUINARY_TDM_RX_6, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) QUINARY_TDM_TX_6, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) QUINARY_TDM_RX_7, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) QUINARY_TDM_TX_7, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DISPLAY_PORT_RX, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) WSA_CODEC_DMA_RX_0, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) WSA_CODEC_DMA_TX_0, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) WSA_CODEC_DMA_RX_1, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) WSA_CODEC_DMA_TX_1, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) WSA_CODEC_DMA_TX_2, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) VA_CODEC_DMA_TX_0, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) [VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) VA_CODEC_DMA_TX_1, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) VA_CODEC_DMA_TX_2, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) RX_CODEC_DMA_RX_0, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) TX_CODEC_DMA_TX_0, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) RX_CODEC_DMA_RX_1, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) TX_CODEC_DMA_TX_1, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) RX_CODEC_DMA_RX_2, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) TX_CODEC_DMA_TX_2, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) [RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) RX_CODEC_DMA_RX_3, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) [TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) TX_CODEC_DMA_TX_3, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) [RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) RX_CODEC_DMA_RX_4, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) [TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) TX_CODEC_DMA_TX_4, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) RX_CODEC_DMA_RX_5, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) [TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) TX_CODEC_DMA_TX_5, 0, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) [RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) RX_CODEC_DMA_RX_6, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) [RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RX_CODEC_DMA_RX_7, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static void q6afe_port_free(struct kref *ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct q6afe_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct q6afe *afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) port = container_of(ref, struct q6afe_port, refcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) afe = port->afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) spin_lock_irqsave(&afe->port_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) list_del(&port->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) spin_unlock_irqrestore(&afe->port_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) kfree(port->scfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) kfree(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct q6afe_port *p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct q6afe_port *ret = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) spin_lock_irqsave(&afe->port_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) list_for_each_entry(p, &afe->port_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (p->token == token) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) kref_get(&p->refcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) spin_unlock_irqrestore(&afe->port_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct q6afe *afe = dev_get_drvdata(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct aprv2_ibasic_rsp_result_t *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct apr_hdr *hdr = &data->hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct q6afe_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!data->payload_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) res = data->payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) switch (hdr->opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case APR_BASIC_RSP_RESULT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (res->status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_err(afe->dev, "cmd = 0x%x returned error = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) res->opcode, res->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) switch (res->opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case AFE_PORT_CMD_SET_PARAM_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case AFE_PORT_CMD_DEVICE_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case AFE_PORT_CMD_DEVICE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case AFE_SVC_CMD_SET_PARAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) port = q6afe_find_port(afe, hdr->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) port->result = *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) wake_up(&port->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) kref_put(&port->refcount, q6afe_port_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) } else if (hdr->token == AFE_CLK_TOKEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) afe->result = *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) wake_up(&afe->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev_err(afe->dev, "Unknown cmd 0x%x\n", res->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) afe->result.opcode = hdr->opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) afe->result.status = res->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) wake_up(&afe->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * q6afe_get_port_id() - Get port id from a given port index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * @index: port index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * Return: Will be an negative on error or valid port_id on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int q6afe_get_port_id(int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (index < 0 || index >= AFE_PORT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return port_maps[index].port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) EXPORT_SYMBOL_GPL(q6afe_get_port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct q6afe_port *port, uint32_t rsp_opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) wait_queue_head_t *wait = &port->wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct aprv2_ibasic_rsp_result_t *result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) mutex_lock(&afe->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) wait = &port->wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) result = &port->result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) result = &afe->result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) wait = &afe->wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) result->opcode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) result->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = apr_send_pkt(afe->apr, pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev_err(afe->dev, "packet not transmitted (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = wait_event_timeout(*wait, (result->opcode == rsp_opcode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) msecs_to_jiffies(TIMEOUT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) } else if (result->status > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev_err(afe->dev, "DSP returned error[%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) result->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) mutex_unlock(&afe->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) void *data, int param_id, int module_id, int psize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) int token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct afe_svc_cmd_set_param *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct afe_port_param_data_v2 *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct apr_pkt *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int ret, pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) void *p, *pl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) p = kzalloc(pkt_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) pkt = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) param = p + APR_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) pdata = p + APR_HDR_SIZE + sizeof(*param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) memcpy(pl, data, psize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) APR_HDR_LEN(APR_HDR_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) APR_PKT_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) pkt->hdr.pkt_size = pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pkt->hdr.src_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pkt->hdr.dest_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) pkt->hdr.token = token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) param->payload_size = sizeof(*pdata) + psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) param->payload_address_lsw = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) param->payload_address_msw = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) param->mem_map_handle = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) pdata->module_id = module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) pdata->param_id = param_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) pdata->param_size = psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_err(afe->dev, "AFE set params failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) kfree(pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int q6afe_port_set_param(struct q6afe_port *port, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) int param_id, int module_id, int psize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return q6afe_set_param(port->afe, port, data, param_id, module_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) psize, port->token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int param_id, int module_id, int psize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct afe_port_cmd_set_param_v2 *param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct afe_port_param_data_v2 *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct q6afe *afe = port->afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct apr_pkt *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) u16 port_id = port->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) int ret, pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) void *p, *pl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) p = kzalloc(pkt_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) pkt = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) param = p + APR_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) pdata = p + APR_HDR_SIZE + sizeof(*param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) memcpy(pl, data, psize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) APR_HDR_LEN(APR_HDR_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) APR_PKT_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) pkt->hdr.pkt_size = pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) pkt->hdr.src_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) pkt->hdr.dest_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) pkt->hdr.token = port->token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pkt->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) param->port_id = port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) param->payload_size = sizeof(*pdata) + psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) param->payload_address_lsw = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) param->payload_address_msw = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) param->mem_map_handle = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) pdata->module_id = module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) pdata->param_id = param_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pdata->param_size = psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_SET_PARAM_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) port_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) kfree(pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static int q6afe_port_set_lpass_clock(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct afe_clk_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return q6afe_port_set_param_v2(port, cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) AFE_PARAM_ID_LPAIF_CLK_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) AFE_MODULE_AUDIO_DEV_INTERFACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int q6afe_set_lpass_clock_v2(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct afe_clk_set *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) AFE_MODULE_CLOCK_SET, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct afe_digital_clk_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return q6afe_port_set_param_v2(port, cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) AFE_MODULE_AUDIO_DEV_INTERFACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int clk_root, unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct q6afe *afe = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct afe_clk_set cset = {0,};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) cset.clk_id = clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) cset.clk_freq_in_hz = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) cset.clk_attri = attri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) cset.clk_root = clk_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) cset.enable = !!freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) AFE_MODULE_CLOCK_SET, sizeof(cset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) AFE_CLK_TOKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int clk_src, int clk_root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct afe_clk_cfg ccfg = {0,};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct afe_clk_set cset = {0,};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct afe_digital_clk_cfg dcfg = {0,};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) case LPAIF_DIG_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dcfg.clk_val = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) dcfg.clk_root = clk_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ret = q6afe_set_digital_codec_core_clock(port, &dcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) case LPAIF_BIT_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) ccfg.clk_val1 = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ccfg.clk_src = clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ccfg.clk_root = clk_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ret = q6afe_port_set_lpass_clock(port, &ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) case LPAIF_OSR_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ccfg.clk_val2 = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ccfg.clk_src = clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ccfg.clk_root = clk_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = q6afe_port_set_lpass_clock(port, &ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) cset.clk_id = clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) cset.clk_freq_in_hz = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) cset.clk_attri = clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) cset.clk_root = clk_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) cset.enable = !!freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ret = q6afe_set_lpass_clock_v2(port, &cset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) EXPORT_SYMBOL_GPL(q6afe_port_set_sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * q6afe_port_stop() - Stop a afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * @port: Instance of port to stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * Return: Will be an negative on packet size on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) int q6afe_port_stop(struct q6afe_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct afe_port_cmd_device_stop *stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct q6afe *afe = port->afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct apr_pkt *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) int port_id = port->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) int index, pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) port_id = port->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) index = port->token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (index < 0 || index >= AFE_PORT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) dev_err(afe->dev, "AFE port index[%d] invalid!\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pkt_size = APR_HDR_SIZE + sizeof(*stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) p = kzalloc(pkt_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) pkt = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) stop = p + APR_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) APR_HDR_LEN(APR_HDR_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) APR_PKT_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) pkt->hdr.pkt_size = pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pkt->hdr.src_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) pkt->hdr.dest_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) pkt->hdr.token = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) stop->port_id = port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) stop->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dev_err(afe->dev, "AFE close failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) kfree(pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) EXPORT_SYMBOL_GPL(q6afe_port_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * q6afe_slim_port_prepare() - Prepare slim afe port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * @port: Instance of afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * @cfg: SLIM configuration for the afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) void q6afe_slim_port_prepare(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct q6afe_slim_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) union afe_port_config *pcfg = &port->port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) pcfg->slim_cfg.sample_rate = cfg->sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) pcfg->slim_cfg.bit_width = cfg->bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) pcfg->slim_cfg.num_channels = cfg->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) pcfg->slim_cfg.data_format = cfg->data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * q6afe_tdm_port_prepare() - Prepare tdm afe port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * @port: Instance of afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * @cfg: TDM configuration for the afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) void q6afe_tdm_port_prepare(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct q6afe_tdm_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) union afe_port_config *pcfg = &port->port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) pcfg->tdm_cfg.num_channels = cfg->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) pcfg->tdm_cfg.sample_rate = cfg->sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) pcfg->tdm_cfg.bit_width = cfg->bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) pcfg->tdm_cfg.data_format = cfg->data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) pcfg->tdm_cfg.sync_mode = cfg->sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) pcfg->tdm_cfg.sync_src = cfg->sync_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) pcfg->tdm_cfg.slot_width = cfg->slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) pcfg->tdm_cfg.slot_mask = cfg->slot_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) port->scfg = kzalloc(sizeof(*port->scfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (!port->scfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) port->scfg->num_channels = cfg->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) port->scfg->bitwidth = cfg->bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) port->scfg->data_align_type = cfg->data_align_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) memcpy(port->scfg->ch_mapping, cfg->ch_mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * q6afe_hdmi_port_prepare() - Prepare hdmi afe port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * @port: Instance of afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * @cfg: HDMI configuration for the afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) void q6afe_hdmi_port_prepare(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct q6afe_hdmi_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) union afe_port_config *pcfg = &port->port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) pcfg->hdmi_multi_ch.hdmi_cfg_minor_version =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) AFE_API_VERSION_HDMI_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) pcfg->hdmi_multi_ch.datatype = cfg->datatype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) pcfg->hdmi_multi_ch.bit_width = cfg->bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) EXPORT_SYMBOL_GPL(q6afe_hdmi_port_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * q6afe_i2s_port_prepare() - Prepare i2s afe port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * @port: Instance of afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * @cfg: I2S configuration for the afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * Return: Will be an negative on error and zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) union afe_port_config *pcfg = &port->port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct device *dev = port->afe->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int num_sd_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) pcfg->i2s_cfg.sample_rate = cfg->sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) pcfg->i2s_cfg.bit_width = cfg->bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) switch (cfg->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* CPU is slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) num_sd_lines = hweight_long(cfg->sd_line_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) switch (num_sd_lines) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dev_err(dev, "no line is assigned\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) switch (cfg->sd_line_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) case AFE_PORT_I2S_SD0_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) case AFE_PORT_I2S_SD1_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) case AFE_PORT_I2S_SD2_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) case AFE_PORT_I2S_SD3_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dev_err(dev, "Invalid SD lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) switch (cfg->sd_line_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) case AFE_PORT_I2S_SD0_1_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) case AFE_PORT_I2S_SD2_3_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(dev, "Invalid SD lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) switch (cfg->sd_line_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) case AFE_PORT_I2S_SD0_1_2_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) dev_err(dev, "Invalid SD lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) switch (cfg->sd_line_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) case AFE_PORT_I2S_SD0_1_2_3_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) dev_err(dev, "Invalid SD lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) dev_err(dev, "Invalid SD lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) switch (cfg->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) switch (pcfg->i2s_cfg.channel_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) case AFE_PORT_I2S_QUAD01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) case AFE_PORT_I2S_6CHS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) case AFE_PORT_I2S_8CHS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) case AFE_PORT_I2S_QUAD23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (cfg->num_channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dev_err(dev, "Invalid Channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) dev_err(dev, "Invalid Channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) dev_err(dev, "Invalid Channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * q6afe_dam_port_prepare() - Prepare dma afe port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * @port: Instance of afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * @cfg: DMA configuration for the afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct q6afe_cdc_dma_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) union afe_port_config *pcfg = &port->port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) dma_cfg->sample_rate = cfg->sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) dma_cfg->bit_width = cfg->bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) dma_cfg->data_format = cfg->data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dma_cfg->num_channels = cfg->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (!cfg->active_channels_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * q6afe_port_start() - Start a afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * @port: Instance of port to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) * Return: Will be an negative on packet size on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int q6afe_port_start(struct q6afe_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct afe_port_cmd_device_start *start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct q6afe *afe = port->afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) int port_id = port->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) int ret, param_id = port->cfg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct apr_pkt *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) int pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) ret = q6afe_port_set_param_v2(port, &port->port_cfg, param_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) AFE_MODULE_AUDIO_DEV_INTERFACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) sizeof(port->port_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) port_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (port->scfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ret = q6afe_port_set_param_v2(port, port->scfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) AFE_MODULE_TDM, sizeof(*port->scfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) port_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) pkt_size = APR_HDR_SIZE + sizeof(*start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) p = kzalloc(pkt_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) pkt = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) start = p + APR_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) APR_HDR_LEN(APR_HDR_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) APR_PKT_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) pkt->hdr.pkt_size = pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) pkt->hdr.src_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) pkt->hdr.dest_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) pkt->hdr.token = port->token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) start->port_id = port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) port_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) kfree(pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) EXPORT_SYMBOL_GPL(q6afe_port_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * q6afe_port_get_from_id() - Get port instance from a port id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * @dev: Pointer to afe child device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * @id: port id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * Return: Will be an error pointer on error or a valid afe port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) struct q6afe *afe = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct q6afe_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) int cfg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (id < 0 || id >= AFE_PORT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) dev_err(dev, "AFE port token[%d] invalid!\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* if port is multiple times bind/unbind before callback finishes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) port = q6afe_find_port(afe, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) dev_err(dev, "AFE Port already open\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) port_id = port_maps[id].port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) switch (port_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) case AFE_PORT_ID_MULTICHAN_HDMI_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) case AFE_PORT_ID_HDMI_OVER_DP_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) cfg_type = AFE_PARAM_ID_HDMI_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) case AFE_PORT_ID_PRIMARY_MI2S_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) case AFE_PORT_ID_PRIMARY_MI2S_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) case AFE_PORT_ID_SECONDARY_MI2S_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) case AFE_PORT_ID_SECONDARY_MI2S_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) case AFE_PORT_ID_TERTIARY_MI2S_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) case AFE_PORT_ID_TERTIARY_MI2S_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) case AFE_PORT_ID_QUATERNARY_MI2S_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case AFE_PORT_ID_QUATERNARY_MI2S_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) cfg_type = AFE_PARAM_ID_I2S_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) cfg_type = AFE_PARAM_ID_TDM_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) dev_err(dev, "Invalid port id 0x%x\n", port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) port = kzalloc(sizeof(*port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) init_waitqueue_head(&port->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) port->token = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) port->id = port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) port->afe = afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) port->cfg_type = cfg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) kref_init(&port->refcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) spin_lock_irqsave(&afe->port_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) list_add_tail(&port->node, &afe->port_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) spin_unlock_irqrestore(&afe->port_list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) EXPORT_SYMBOL_GPL(q6afe_port_get_from_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * q6afe_port_put() - Release port reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * @port: Instance of port to put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) void q6afe_port_put(struct q6afe_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) kref_put(&port->refcount, q6afe_port_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) EXPORT_SYMBOL_GPL(q6afe_port_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) uint32_t client_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct q6afe *afe = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct afe_cmd_remote_lpass_core_hw_devote_request *vote_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct apr_pkt *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) int pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) p = kzalloc(pkt_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) pkt = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) vote_cfg = p + APR_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) APR_HDR_LEN(APR_HDR_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) APR_PKT_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) pkt->hdr.pkt_size = pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) pkt->hdr.src_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) pkt->hdr.dest_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) pkt->hdr.token = hw_block_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) vote_cfg->hw_block_id = hw_block_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) vote_cfg->client_handle = client_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ret = apr_send_pkt(afe->apr, pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) dev_err(afe->dev, "AFE failed to unvote (%d)\n", hw_block_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) kfree(pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) EXPORT_SYMBOL(q6afe_unvote_lpass_core_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) char *client_name, uint32_t *client_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) struct q6afe *afe = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) struct afe_cmd_remote_lpass_core_hw_vote_request *vote_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) struct apr_pkt *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) int pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) p = kzalloc(pkt_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) pkt = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) vote_cfg = p + APR_HDR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) APR_HDR_LEN(APR_HDR_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) APR_PKT_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) pkt->hdr.pkt_size = pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) pkt->hdr.src_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) pkt->hdr.dest_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) pkt->hdr.token = hw_block_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) vote_cfg->hw_block_id = hw_block_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) strlcpy(vote_cfg->client_name, client_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) sizeof(vote_cfg->client_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ret = afe_apr_send_pkt(afe, pkt, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) dev_err(afe->dev, "AFE failed to vote (%d)\n", hw_block_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) kfree(pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) EXPORT_SYMBOL(q6afe_vote_lpass_core_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static int q6afe_probe(struct apr_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct q6afe *afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) struct device *dev = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (!afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) q6core_get_svc_api_info(adev->svc_id, &afe->ainfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) afe->apr = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) mutex_init(&afe->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) init_waitqueue_head(&afe->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) afe->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) INIT_LIST_HEAD(&afe->port_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) spin_lock_init(&afe->port_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) dev_set_drvdata(dev, afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return of_platform_populate(dev->of_node, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static int q6afe_remove(struct apr_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) of_platform_depopulate(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static const struct of_device_id q6afe_device_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) { .compatible = "qcom,q6afe" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) MODULE_DEVICE_TABLE(of, q6afe_device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static struct apr_driver qcom_q6afe_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .probe = q6afe_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .remove = q6afe_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .callback = q6afe_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .name = "qcom-q6afe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .of_match_table = of_match_ptr(q6afe_device_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) module_apr_driver(qcom_q6afe_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) MODULE_DESCRIPTION("Q6 Audio Front End");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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