^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2020, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "q6afe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define Q6AFE_CLK(id) &(struct q6afe_clk) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .clk_id = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .afe_clk_id = Q6AFE_##id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .name = #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .attributes = LPASS_CLK_ATTRIBUTE_COUPLE_NO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .rate = 19200000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .ops = &clk_q6afe_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .name = #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define Q6AFE_VOTE_CLK(id, blkid, n) &(struct q6afe_clk) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .clk_id = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .afe_clk_id = blkid, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = #n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .hw.init = &(struct clk_init_data) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .ops = &clk_vote_q6afe_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .name = #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct q6afe_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int afe_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int attributes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define to_q6afe_clk(_hw) container_of(_hw, struct q6afe_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct q6afe_cc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct q6afe_clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int clk_q6afe_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct q6afe_clk *clk = to_q6afe_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Q6AFE_LPASS_CLK_ROOT_DEFAULT, clk->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void clk_q6afe_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct q6afe_clk *clk = to_q6afe_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Q6AFE_LPASS_CLK_ROOT_DEFAULT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int clk_q6afe_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct q6afe_clk *clk = to_q6afe_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clk->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static unsigned long clk_q6afe_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct q6afe_clk *clk = to_q6afe_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static long clk_q6afe_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct clk_ops clk_q6afe_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .prepare = clk_q6afe_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .unprepare = clk_q6afe_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .set_rate = clk_q6afe_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .round_rate = clk_q6afe_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .recalc_rate = clk_q6afe_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int clk_vote_q6afe_block(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct q6afe_clk *clk = to_q6afe_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return q6afe_vote_lpass_core_hw(clk->dev, clk->afe_clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk->name, &clk->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void clk_unvote_q6afe_block(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct q6afe_clk *clk = to_q6afe_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) q6afe_unvote_lpass_core_hw(clk->dev, clk->afe_clk_id, clk->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct clk_ops clk_vote_q6afe_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .prepare = clk_vote_q6afe_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .unprepare = clk_unvote_q6afe_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct q6afe_clk *q6afe_clks[Q6AFE_MAX_CLK_ID] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [LPASS_CLK_ID_PRI_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [LPASS_CLK_ID_PRI_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [LPASS_CLK_ID_SEC_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [LPASS_CLK_ID_SEC_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [LPASS_CLK_ID_TER_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [LPASS_CLK_ID_TER_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [LPASS_CLK_ID_QUAD_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [LPASS_CLK_ID_QUAD_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [LPASS_CLK_ID_SPEAKER_I2S_IBIT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [LPASS_CLK_ID_SPEAKER_I2S_EBIT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [LPASS_CLK_ID_SPEAKER_I2S_OSR] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [LPASS_CLK_ID_QUI_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [LPASS_CLK_ID_QUI_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [LPASS_CLK_ID_SEN_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [LPASS_CLK_ID_SEN_MI2S_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [LPASS_CLK_ID_INT0_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [LPASS_CLK_ID_INT1_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [LPASS_CLK_ID_INT2_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [LPASS_CLK_ID_INT3_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [LPASS_CLK_ID_INT4_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [LPASS_CLK_ID_INT5_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [LPASS_CLK_ID_INT6_MI2S_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [LPASS_CLK_ID_QUI_MI2S_OSR] = Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [LPASS_CLK_ID_PRI_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [LPASS_CLK_ID_PRI_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [LPASS_CLK_ID_SEC_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [LPASS_CLK_ID_SEC_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [LPASS_CLK_ID_TER_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [LPASS_CLK_ID_TER_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [LPASS_CLK_ID_QUAD_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [LPASS_CLK_ID_QUAD_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [LPASS_CLK_ID_QUIN_PCM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [LPASS_CLK_ID_QUIN_PCM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [LPASS_CLK_ID_QUI_PCM_OSR] = Q6AFE_CLK(LPASS_CLK_ID_QUI_PCM_OSR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [LPASS_CLK_ID_PRI_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [LPASS_CLK_ID_PRI_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [LPASS_CLK_ID_SEC_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [LPASS_CLK_ID_SEC_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [LPASS_CLK_ID_TER_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [LPASS_CLK_ID_TER_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [LPASS_CLK_ID_QUAD_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [LPASS_CLK_ID_QUAD_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [LPASS_CLK_ID_QUIN_TDM_IBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_IBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [LPASS_CLK_ID_QUIN_TDM_EBIT] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_EBIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [LPASS_CLK_ID_QUIN_TDM_OSR] = Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_OSR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [LPASS_CLK_ID_MCLK_1] = Q6AFE_CLK(LPASS_CLK_ID_MCLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [LPASS_CLK_ID_MCLK_2] = Q6AFE_CLK(LPASS_CLK_ID_MCLK_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [LPASS_CLK_ID_MCLK_3] = Q6AFE_CLK(LPASS_CLK_ID_MCLK_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [LPASS_CLK_ID_MCLK_4] = Q6AFE_CLK(LPASS_CLK_ID_MCLK_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) Q6AFE_CLK(LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [LPASS_CLK_ID_INT_MCLK_0] = Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [LPASS_CLK_ID_INT_MCLK_1] = Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [LPASS_CLK_ID_WSA_CORE_MCLK] = Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [LPASS_CLK_ID_WSA_CORE_NPL_MCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [LPASS_CLK_ID_VA_CORE_MCLK] = Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [LPASS_CLK_ID_TX_CORE_MCLK] = Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [LPASS_CLK_ID_TX_CORE_NPL_MCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [LPASS_CLK_ID_RX_CORE_MCLK] = Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [LPASS_CLK_ID_RX_CORE_NPL_MCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [LPASS_CLK_ID_VA_CORE_2X_MCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [LPASS_HW_AVTIMER_VOTE] = Q6AFE_VOTE_CLK(LPASS_HW_AVTIMER_VOTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) Q6AFE_LPASS_CORE_AVTIMER_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "LPASS_AVTIMER_MACRO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [LPASS_HW_MACRO_VOTE] = Q6AFE_VOTE_CLK(LPASS_HW_MACRO_VOTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) Q6AFE_LPASS_CORE_HW_MACRO_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "LPASS_HW_MACRO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [LPASS_HW_DCODEC_VOTE] = Q6AFE_VOTE_CLK(LPASS_HW_DCODEC_VOTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "LPASS_HW_DCODEC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct clk_hw *q6afe_of_clk_hw_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct q6afe_cc *cc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int attr = clkspec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (idx >= cc->num_clks || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (cc->clks[idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cc->clks[idx]->attributes = attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return &cc->clks[idx]->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int q6afe_clock_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct q6afe_cc *cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) cc->clks = &q6afe_clks[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cc->num_clks = ARRAY_SIZE(q6afe_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for (i = 0; i < ARRAY_SIZE(q6afe_clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!q6afe_clks[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) q6afe_clks[i]->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = devm_clk_hw_register(dev, &q6afe_clks[i]->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = of_clk_add_hw_provider(dev->of_node, q6afe_of_clk_hw_get, cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_set_drvdata(dev, cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct of_device_id q6afe_clock_device_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { .compatible = "qcom,q6afe-clocks" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_DEVICE_TABLE(of, q6afe_clock_device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct platform_driver q6afe_clock_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .name = "q6afe-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .of_match_table = of_match_ptr(q6afe_clock_device_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .probe = q6afe_clock_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) module_platform_driver(q6afe_clock_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_DESCRIPTION("Q6 Audio Frontend clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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