Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * lpass.h - Definitions for the QTi LPASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __LPASS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __LPASS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <dt-bindings/sound/qcom,lpass.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "lpass-hdmi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define LPASS_AHBIX_CLOCK_FREQUENCY		131072000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LPASS_MAX_MI2S_PORTS			(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LPASS_MAX_DMA_CHANNELS			(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LPASS_MAX_HDMI_DMA_CHANNELS		(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf)    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		mf = devm_regmap_field_alloc(d, m, f);     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		if (IS_ERR(mf))                \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 			return -EINVAL;         \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct lpaif_i2sctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct regmap_field *loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct regmap_field *spken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct regmap_field *spkmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct regmap_field *spkmono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct regmap_field *micen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct regmap_field *micmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct regmap_field *micmono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct regmap_field *wssrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct regmap_field *bitwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct lpaif_dmactl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct regmap_field *intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct regmap_field *bursten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct regmap_field *wpscnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct regmap_field *fifowm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct regmap_field *enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct regmap_field *dyncclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct regmap_field *burst8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct regmap_field *burst16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct regmap_field *dynburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Both the CPU DAI and platform drivers will access this data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct lpass_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct clk *ahbix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* MI2S system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/* MI2S bit clock (derived from system clock by a divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* MI2S SD lines to use for playback/capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/* The state of MI2S prepare dai_ops was called */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	bool mi2s_was_prepared[LPASS_MAX_MI2S_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int hdmi_port_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* low-power audio interface (LPAIF) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	void __iomem *lpaif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	void __iomem *hdmiif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* regmap backed by the low-power audio interface (LPAIF) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct regmap *lpaif_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct regmap *hdmiif_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* interrupts from the low-power audio interface (LPAIF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int lpaif_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int hdmiif_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* SOC specific variations in the LPASS IP integration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct lpass_variant *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* bit map to keep track of static channel allocations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	unsigned long dma_ch_bit_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned long hdmi_dma_ch_bit_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* used it for handling interrupt per dma channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* SOC specific clock list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* Regmap fields of I2SCTL & DMACTL registers bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct lpaif_i2sctl *i2sctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct lpaif_dmactl *rd_dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct lpaif_dmactl *wr_dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct lpaif_dmactl *hdmi_rd_dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* Regmap fields of HDMI_CTRL registers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct regmap_field *hdmitx_legacy_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct regmap_field *hdmitx_parity_calc_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct lpass_hdmi_tx_ctl *tx_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct lpass_vbit_ctrl *vbit_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct lpass_dp_metadata_ctl *meta_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct lpass_sstream_ctl *sstream_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Vairant data per each SOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct lpass_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32	irq_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32	irq_reg_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u32	irq_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32	rdma_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32	rdma_reg_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u32	rdma_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u32	hdmi_rdma_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32	hdmi_rdma_reg_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32	hdmi_rdma_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32	wrdma_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u32	wrdma_reg_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32	wrdma_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32	i2sctrl_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32	i2sctrl_reg_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u32	i2s_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/* I2SCTL Register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct reg_field loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct reg_field spken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct reg_field spkmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct reg_field spkmono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct reg_field micen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct reg_field micmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct reg_field micmono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct reg_field wssrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct reg_field bitwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32	hdmi_irq_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u32	hdmi_irq_reg_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u32	hdmi_irq_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* HDMI specific controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u32	hdmi_tx_ctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32	hdmi_legacy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32	hdmi_vbit_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32	hdmi_ch_lsb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u32	hdmi_ch_msb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32	ch_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32	hdmi_parity_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u32	hdmi_dmactl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u32	hdmi_dma_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u32	hdmi_DP_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32	hdmi_sstream_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* HDMI SSTREAM CTRL fields  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct reg_field sstream_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct reg_field dma_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct reg_field auto_bbit_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct reg_field layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct reg_field layout_sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct reg_field set_sp_on_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct reg_field dp_audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct reg_field dp_staffing_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct reg_field dp_sp_b_hw_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* HDMI DP METADATA CTL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct reg_field mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct reg_field as_sdp_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct reg_field as_sdp_ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct reg_field aif_db4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct reg_field frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct reg_field mst_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct reg_field dptx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* HDMI TX CTRL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct reg_field soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct reg_field force_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* HDMI TX DMA CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct reg_field use_hw_chs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct reg_field use_hw_usr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct reg_field hw_chs_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct reg_field hw_usr_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* HDMI VBIT CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct reg_field replace_vbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct reg_field vbit_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* HDMI TX LEGACY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct reg_field legacy_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* HDMI TX PARITY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct reg_field calc_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* HDMI CH LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct reg_field lsb_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* HDMI CH MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct reg_field msb_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct reg_field hdmi_rdma_bursten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct reg_field hdmi_rdma_wpscnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct reg_field hdmi_rdma_fifowm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct reg_field hdmi_rdma_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct reg_field hdmi_rdma_dyncclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct reg_field hdmi_rdma_burst8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct reg_field hdmi_rdma_burst16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct reg_field hdmi_rdma_dynburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/* RD_DMA Register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct reg_field rdma_intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct reg_field rdma_bursten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct reg_field rdma_wpscnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct reg_field rdma_fifowm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct reg_field rdma_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct reg_field rdma_dyncclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* WR_DMA Register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct reg_field wrdma_intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct reg_field wrdma_bursten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct reg_field wrdma_wpscnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct reg_field wrdma_fifowm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct reg_field wrdma_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct reg_field wrdma_dyncclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * on SOCs like APQ8016 the channel control bits start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * at different offset to ipq806x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u32	dmactl_audif_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	u32	wrdma_channel_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* SOC specific initialization like clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int (*init)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int (*exit)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* SOC specific dais */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct snd_soc_dai_driver *dai_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int num_dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	const char * const *dai_osr_clk_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	const char * const *dai_bit_clk_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* SOC specific clocks configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	const char **clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* register the platform driver from the CPU DAI driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int asoc_qcom_lpass_platform_register(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif /* __LPASS_H__ */