Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <dt-bindings/sound/sc7180-lpass.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "lpass-lpaif-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "lpass.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static struct snd_soc_dai_driver sc7180_lpass_cpu_dai_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		.id = MI2S_PRIMARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.name = "Primary MI2S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 			.stream_name = "Primary Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 			.formats	= SNDRV_PCM_FMTBIT_S16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 			.rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 			.rate_min	= 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			.rate_max	= 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			.channels_max	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 			.stream_name = "Primary Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			.formats = SNDRV_PCM_FMTBIT_S16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			.rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			.rate_min	= 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 			.rate_max	= 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			.channels_max	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.probe	= &asoc_qcom_lpass_cpu_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.ops    = &asoc_qcom_lpass_cpu_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.id = MI2S_SECONDARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.name = "Secondary MI2S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			.stream_name = "Secondary Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			.formats	= SNDRV_PCM_FMTBIT_S16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			.rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			.rate_min	= 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			.rate_max	= 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			.channels_max	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.probe	= &asoc_qcom_lpass_cpu_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.ops    = &asoc_qcom_lpass_cpu_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.id = LPASS_DP_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.name = "Hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			.stream_name = "Hdmi Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			.formats	= SNDRV_PCM_FMTBIT_S24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			.rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			.rate_min	= 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			.rate_max	= 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			.channels_min	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			.channels_max	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.ops    = &asoc_qcom_lpass_hdmi_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int sc7180_lpass_alloc_dma_channel(struct lpass_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					   int direction, unsigned int dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (dai_id == LPASS_DP_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 						v->hdmi_rdma_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			if (chan >= v->hdmi_rdma_channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 				return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 						v->rdma_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		if (chan >= v->rdma_channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 					v->wrdma_channel_start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					v->wrdma_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					v->wrdma_channel_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			if (chan >=  v->wrdma_channel_start + v->wrdma_channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		set_bit(chan, &drvdata->dma_ch_bit_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int sc7180_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (dai_id == LPASS_DP_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		clear_bit(chan, &drvdata->dma_ch_bit_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int sc7180_lpass_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct lpass_data *drvdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct lpass_variant *variant = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	drvdata->clks = devm_kcalloc(dev, variant->num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				     sizeof(*drvdata->clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	drvdata->num_clks = variant->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	for (i = 0; i < drvdata->num_clks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		drvdata->clks[i].id = variant->clk_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		dev_err(dev, "Failed to get clocks %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		dev_err(dev, "sc7180 clk_enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int sc7180_lpass_exit(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct lpass_data *drvdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct lpass_variant sc7180_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.i2sctrl_reg_base	= 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.i2sctrl_reg_stride	= 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.i2s_ports		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.irq_reg_base		= 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.irq_reg_stride		= 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.irq_ports		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.rdma_reg_base		= 0xC000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.rdma_reg_stride	= 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.rdma_channels		= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.hdmi_rdma_reg_base		= 0x64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.hdmi_rdma_reg_stride	= 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.hdmi_rdma_channels		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.dmactl_audif_start	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.wrdma_reg_base		= 0x18000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.wrdma_reg_stride	= 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.wrdma_channel_start	= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.wrdma_channels		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.loopback		= REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.spken			= REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.spkmode		= REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.spkmono		= REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.micen			= REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.micmode		= REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.micmono		= REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.wssrc			= REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.bitwidth		= REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.rdma_dyncclk		= REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.rdma_bursten		= REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.rdma_wpscnt		= REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.rdma_intf			= REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.rdma_fifowm		= REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.rdma_enable		= REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.wrdma_dyncclk		= REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.wrdma_bursten		= REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.wrdma_wpscnt		= REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.wrdma_intf		= REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.wrdma_fifowm		= REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.wrdma_enable		= REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.hdmi_tx_ctl_addr	= 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.hdmi_legacy_addr	= 0x1008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.hdmi_vbit_addr		= 0x610c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.hdmi_ch_lsb_addr	= 0x61048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.hdmi_ch_msb_addr	= 0x6104c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.ch_stride		= 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.hdmi_parity_addr	= 0x61034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.hdmi_dmactl_addr	= 0x61038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.hdmi_dma_stride	= 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.hdmi_DP_addr		= 0x610c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.hdmi_sstream_addr	= 0x6101c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.hdmi_irq_reg_base		= 0x63000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.hdmi_irq_ports		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.hdmi_rdma_dyncclk		= REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.hdmi_rdma_bursten		= REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.hdmi_rdma_burst8		= REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.hdmi_rdma_burst16		= REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.hdmi_rdma_dynburst		= REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.hdmi_rdma_wpscnt		= REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.hdmi_rdma_fifowm		= REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.hdmi_rdma_enable		= REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.sstream_en		= REG_FIELD(0x6101c, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.dma_sel			= REG_FIELD(0x6101c, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.auto_bbit_en	= REG_FIELD(0x6101c, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.layout			= REG_FIELD(0x6101c, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.layout_sp		= REG_FIELD(0x6101c, 5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.set_sp_on_en	= REG_FIELD(0x6101c, 10, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.dp_audio		= REG_FIELD(0x6101c, 11, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.dp_staffing_en	= REG_FIELD(0x6101c, 12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.dp_sp_b_hw_en	= REG_FIELD(0x6101c, 13, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.mute			= REG_FIELD(0x610c8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.as_sdp_cc		= REG_FIELD(0x610c8, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.as_sdp_ct		= REG_FIELD(0x610c8, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.aif_db4			= REG_FIELD(0x610c8, 8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.frequency		= REG_FIELD(0x610c8, 16, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.mst_index		= REG_FIELD(0x610c8, 28, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.dptx_index		= REG_FIELD(0x610c8, 30, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.soft_reset		= REG_FIELD(0x1000, 31, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.force_reset	= REG_FIELD(0x1000, 30, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.use_hw_chs		= REG_FIELD(0x61038, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.use_hw_usr		= REG_FIELD(0x61038, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.hw_chs_sel		= REG_FIELD(0x61038, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.hw_usr_sel		= REG_FIELD(0x61038, 5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.replace_vbit	= REG_FIELD(0x610c0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.vbit_stream	= REG_FIELD(0x610c0, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.legacy_en		=  REG_FIELD(0x1008, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.calc_en		=  REG_FIELD(0x61034, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.lsb_bits		=  REG_FIELD(0x61048, 0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.msb_bits		=  REG_FIELD(0x6104c, 0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.clk_name		= (const char*[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				   "pcnoc-sway-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				   "audio-core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				   "pcnoc-mport-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.num_clks		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.dai_driver		= sc7180_lpass_cpu_dai_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.num_dai		= ARRAY_SIZE(sc7180_lpass_cpu_dai_driver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.dai_osr_clk_names      = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				   "mclk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				   "null",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 				},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.dai_bit_clk_names      = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				   "mi2s-bit-clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				   "mi2s-bit-clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.init			= sc7180_lpass_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.exit			= sc7180_lpass_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.alloc_dma_channel	= sc7180_lpass_alloc_dma_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.free_dma_channel	= sc7180_lpass_free_dma_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct of_device_id sc7180_lpass_cpu_device_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	{.compatible = "qcom,sc7180-lpass-cpu", .data = &sc7180_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_DEVICE_TABLE(of, sc7180_lpass_cpu_device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct platform_driver sc7180_lpass_cpu_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.name = "sc7180-lpass-cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.of_match_table = of_match_ptr(sc7180_lpass_cpu_device_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.probe = asoc_qcom_lpass_cpu_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.remove = asoc_qcom_lpass_cpu_platform_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) module_platform_driver(sc7180_lpass_cpu_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_DESCRIPTION("SC7180 LPASS CPU DRIVER");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_LICENSE("GPL v2");