Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __LPASS_LPAIF_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __LPASS_LPAIF_REG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /* LPAIF I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	(v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define LPAIF_I2SCTL_REG(v, port)	LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define LPAIF_I2SCTL_LOOPBACK_DISABLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define LPAIF_I2SCTL_LOOPBACK_ENABLE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LPAIF_I2SCTL_SPKEN_DISABLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LPAIF_I2SCTL_SPKEN_ENABLE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LPAIF_I2SCTL_MODE_NONE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LPAIF_I2SCTL_MODE_SD0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LPAIF_I2SCTL_MODE_SD1		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LPAIF_I2SCTL_MODE_SD2		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LPAIF_I2SCTL_MODE_SD3		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LPAIF_I2SCTL_MODE_QUAD01	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LPAIF_I2SCTL_MODE_QUAD23	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LPAIF_I2SCTL_MODE_6CH		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LPAIF_I2SCTL_MODE_8CH		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LPAIF_I2SCTL_MODE_10CH		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LPAIF_I2SCTL_MODE_12CH		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LPAIF_I2SCTL_MODE_14CH		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LPAIF_I2SCTL_MODE_16CH		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LPAIF_I2SCTL_MODE_SD4		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LPAIF_I2SCTL_MODE_SD5		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LPAIF_I2SCTL_MODE_SD6		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LPAIF_I2SCTL_MODE_SD7		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LPAIF_I2SCTL_MODE_QUAD45	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LPAIF_I2SCTL_MODE_QUAD47	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define LPAIF_I2SCTL_MODE_8CH_2		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define LPAIF_I2SCTL_SPKMODE(mode)	mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define LPAIF_I2SCTL_SPKMONO_STEREO	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define LPAIF_I2SCTL_SPKMONO_MONO	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define LPAIF_I2SCTL_MICEN_DISABLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LPAIF_I2SCTL_MICEN_ENABLE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define LPAIF_I2SCTL_MICMODE(mode)	mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define LPAIF_I2SCTL_MICMONO_STEREO	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define LPAIF_I2SCTL_MICMONO_MONO	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define LPAIF_I2SCTL_WSSRC_INTERNAL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define LPAIF_I2SCTL_WSSRC_EXTERNAL	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define LPAIF_I2SCTL_BITWIDTH_16	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define LPAIF_I2SCTL_BITWIDTH_24	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define LPAIF_I2SCTL_BITWIDTH_32	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define LPAIF_I2SCTL_RESET_STATE	0x003C0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define LPAIF_DMACTL_RESET_STATE	0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* LPAIF IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define LPAIF_IRQ_REG_ADDR(v, addr, port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	(v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define LPAIF_IRQ_PORT_HOST		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define LPAIF_IRQEN_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x0, (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define LPAIF_IRQSTAT_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define LPAIF_IRQCLEAR_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr)  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	((v->hdmi_irq_reg_base) + (addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define LPASS_HDMITX_APP_IRQEN_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define LPASS_HDMITX_APP_IRQSTAT_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define LPASS_HDMITX_APP_IRQCLEAR_REG(v)		LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define LPAIF_IRQ_BITSTRIDE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define LPAIF_IRQ_PER(chan)		(1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define LPAIF_IRQ_XRUN(chan)		(2 << (LPAIF_IRQ_BITSTRIDE * (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define LPAIF_IRQ_ERR(chan)		(4 << (LPAIF_IRQ_BITSTRIDE * (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define LPAIF_IRQ_ALL(chan)		(7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan)	(1 << (14 + chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan)	(1 << (24 + chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define LPAIF_IRQ_HDMI_METADONE		BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* LPAIF DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	(v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LPAIF_HDMI_RDMACTL_AUDINTF(id)	(id << LPAIF_RDMACTL_AUDINTF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LPAIF_HDMI_RDMACTL_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LPAIF_HDMI_RDMABASE_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define	LPAIF_HDMI_RDMABUFF_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LPAIF_HDMI_RDMACURR_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define	LPAIF_HDMI_RDMAPER_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define	LPAIF_HDMI_RDMAPERCNT_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	(v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LPAIF_RDMACTL_AUDINTF(id)	(id << LPAIF_RDMACTL_AUDINTF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LPAIF_RDMACTL_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LPAIF_RDMABASE_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define	LPAIF_RDMABUFF_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LPAIF_RDMACURR_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define	LPAIF_RDMAPER_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define	LPAIF_RDMAPERCNT_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	(v->wrdma_reg_base + (addr) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LPAIF_WRDMACTL_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LPAIF_WRDMABASE_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define	LPAIF_WRDMABUFF_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LPAIF_WRDMACURR_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define	LPAIF_WRDMAPER_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define	LPAIF_WRDMAPERCNT_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LPAIF_INTFDMA_REG(v, chan, reg, dai_id)  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	((dai_id ==  LPASS_DP_RX) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		 LPAIF_RDMA##reg##_REG(v, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id)  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		LPAIF_WRDMA##reg##_REG(v, chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define	LPAIF_DMABUFF_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define	LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PER, dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define	LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LPAIF_DMACTL_BURSTEN_SINGLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LPAIF_DMACTL_BURSTEN_INCR4	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LPAIF_DMACTL_WPSCNT_ONE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LPAIF_DMACTL_WPSCNT_TWO		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LPAIF_DMACTL_WPSCNT_THREE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LPAIF_DMACTL_WPSCNT_FOUR	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LPAIF_DMACTL_WPSCNT_SIX		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LPAIF_DMACTL_WPSCNT_EIGHT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LPAIF_DMACTL_WPSCNT_TEN		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LPAIF_DMACTL_WPSCNT_TWELVE	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LPAIF_DMACTL_WPSCNT_FOURTEEN	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LPAIF_DMACTL_WPSCNT_SIXTEEN	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LPAIF_DMACTL_AUDINTF(id)	id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LPAIF_DMACTL_FIFOWM_1		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LPAIF_DMACTL_FIFOWM_2		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LPAIF_DMACTL_FIFOWM_3		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LPAIF_DMACTL_FIFOWM_4		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LPAIF_DMACTL_FIFOWM_5		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LPAIF_DMACTL_FIFOWM_6		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define LPAIF_DMACTL_FIFOWM_7		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define LPAIF_DMACTL_FIFOWM_8		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define LPAIF_DMACTL_FIFOWM_9		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define LPAIF_DMACTL_FIFOWM_10		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define LPAIF_DMACTL_FIFOWM_11		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define LPAIF_DMACTL_FIFOWM_12		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define LPAIF_DMACTL_FIFOWM_13		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LPAIF_DMACTL_FIFOWM_14		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define LPAIF_DMACTL_FIFOWM_15		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define LPAIF_DMACTL_FIFOWM_16		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define LPAIF_DMACTL_FIFOWM_17		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define LPAIF_DMACTL_FIFOWM_18		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define LPAIF_DMACTL_FIFOWM_19		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define LPAIF_DMACTL_FIFOWM_20		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define LPAIF_DMACTL_FIFOWM_21		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define LPAIF_DMACTL_FIFOWM_22		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define LPAIF_DMACTL_FIFOWM_23		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LPAIF_DMACTL_FIFOWM_24		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LPAIF_DMACTL_FIFOWM_25		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define LPAIF_DMACTL_FIFOWM_26		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define LPAIF_DMACTL_FIFOWM_27		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LPAIF_DMACTL_FIFOWM_28		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define LPAIF_DMACTL_FIFOWM_29		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define LPAIF_DMACTL_FIFOWM_30		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define LPAIF_DMACTL_FIFOWM_31		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define LPAIF_DMACTL_FIFOWM_32		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LPAIF_DMACTL_ENABLE_OFF		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LPAIF_DMACTL_ENABLE_ON		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define LPAIF_DMACTL_DYNCLK_OFF		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LPAIF_DMACTL_DYNCLK_ON		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif /* __LPASS_LPAIF_REG_H__ */