^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * lpass_hdmi.h - Definitions for the QTi LPASS HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __LPASS_HDMI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __LPASS_HDMI_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LPASS_HDMITX_LEGACY_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LPASS_HDMITX_LEGACY_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LPASS_DP_AUDIO_BITWIDTH16 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LPASS_DP_AUDIO_BITWIDTH24 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LPASS_DATA_FORMAT_SHIFT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LPASS_FREQ_BIT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LPASS_DATA_FORMAT_LINEAR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPASS_DATA_FORMAT_NON_LINEAR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPASS_SAMPLING_FREQ32 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPASS_SAMPLING_FREQ44 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPASS_SAMPLING_FREQ48 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LPASS_TX_CTL_RESET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPASS_TX_CTL_CLEAR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPASS_SSTREAM_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPASS_SSTREAM_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPASS_LAYOUT_SP_DEFAULT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPASS_SSTREAM_DEFAULT_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPASS_SSTREAM_DEFAULT_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPASS_MUTE_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPASS_MUTE_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPASS_META_DEFAULT_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HW_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SW_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LEGACY_LPASS_LPAIF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LEGACY_LPASS_HDMI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REPLACE_VBIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LINEAR_PCM_DATA 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NON_LINEAR_PCM_DATA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HDMITX_PARITY_CALC_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HDMITX_PARITY_CALC_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPASS_DATA_FORMAT_MASK GENMASK(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPASS_WORDLENGTH_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPASS_FREQ_BIT_MASK GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPASS_HDMI_TX_CTL_ADDR(v) (v->hdmi_tx_ctl_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPASS_HDMI_TX_LEGACY_ADDR(v) (v->hdmi_legacy_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LPASS_HDMI_TX_VBIT_CTL_ADDR(v) (v->hdmi_vbit_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPASS_HDMI_TX_PARITY_ADDR(v) (v->hdmi_parity_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LPASS_HDMI_TX_DP_ADDR(v) (v->hdmi_DP_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LPASS_HDMI_TX_SSTREAM_ADDR(v) (v->hdmi_sstream_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LPASS_HDMI_TX_CH_LSB_ADDR(v, port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (v->hdmi_ch_lsb_addr + v->ch_stride * (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPASS_HDMI_TX_CH_MSB_ADDR(v, port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (v->hdmi_ch_msb_addr + v->ch_stride * (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LPASS_HDMI_TX_DMA_ADDR(v, port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (v->hdmi_dmactl_addr + v->hdmi_dma_stride * (port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct lpass_sstream_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct regmap_field *sstream_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct regmap_field *dma_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct regmap_field *auto_bbit_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct regmap_field *layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct regmap_field *layout_sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct regmap_field *set_sp_on_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct regmap_field *dp_audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct regmap_field *dp_staffing_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct regmap_field *dp_sp_b_hw_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct lpass_dp_metadata_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct regmap_field *mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct regmap_field *as_sdp_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct regmap_field *as_sdp_ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regmap_field *aif_db4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct regmap_field *frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct regmap_field *mst_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct regmap_field *dptx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct lpass_hdmi_tx_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct regmap_field *soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct regmap_field *force_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct lpass_hdmitx_dmactl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct regmap_field *use_hw_chs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct regmap_field *use_hw_usr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct regmap_field *hw_chs_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct regmap_field *hw_usr_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct lpass_vbit_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct regmap_field *replace_vbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regmap_field *vbit_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) extern const struct snd_soc_dai_ops asoc_qcom_lpass_hdmi_dai_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* __LPASS_HDMI_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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