Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2020 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * lpass-hdmi.c -- ALSA SoC HDMI-CPU DAI driver for QTi LPASS HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <dt-bindings/sound/sc7180-lpass.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "lpass-lpaif-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "lpass.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static int lpass_hdmi_daiops_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	snd_pcm_format_t format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	int bitwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	unsigned int word_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned int ch_sts_buf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned int ch_sts_buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned int data_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	unsigned int sampling_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	unsigned int ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	bitwidth = snd_pcm_format_width(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (bitwidth < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		dev_err(dai->dev, "%s invalid bit width given : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 					__func__, bitwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		return bitwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	switch (bitwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		word_length = LPASS_DP_AUDIO_BITWIDTH16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		word_length = LPASS_DP_AUDIO_BITWIDTH24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		dev_err(dai->dev, "%s invalid bit width given : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 					__func__, bitwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		sampling_freq = LPASS_SAMPLING_FREQ32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		sampling_freq = LPASS_SAMPLING_FREQ44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		sampling_freq = LPASS_SAMPLING_FREQ48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		dev_err(dai->dev, "%s invalid bit width given : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 					__func__, bitwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	data_format = LPASS_DATA_FORMAT_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	ch_sts_buf0 = (((data_format << LPASS_DATA_FORMAT_SHIFT) & LPASS_DATA_FORMAT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				| ((sampling_freq << LPASS_FREQ_BIT_SHIFT) & LPASS_FREQ_BIT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ch_sts_buf1 = (word_length) & LPASS_WORDLENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	ret = regmap_field_write(drvdata->hdmitx_legacy_en, LPASS_HDMITX_LEGACY_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ret = regmap_field_write(drvdata->hdmitx_parity_calc_en, HDMITX_PARITY_CALC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	ret = regmap_field_write(drvdata->vbit_ctl->replace_vbit, REPLACE_VBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	ret = regmap_field_write(drvdata->vbit_ctl->vbit_stream, LINEAR_PCM_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ret = regmap_field_write(drvdata->hdmitx_ch_msb[0], ch_sts_buf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ret = regmap_field_write(drvdata->hdmitx_ch_lsb[0], ch_sts_buf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_chs, HW_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_chs_sel, SW_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_usr, HW_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_usr_sel, SW_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ret = regmap_field_write(meta_ctl->as_sdp_cc, channels - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ret = regmap_field_write(meta_ctl->as_sdp_ct, LPASS_META_DEFAULT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ret = regmap_field_write(meta_ctl->aif_db4, LPASS_META_DEFAULT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ret = regmap_field_write(meta_ctl->frequency, sampling_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ret = regmap_field_write(meta_ctl->mst_index, LPASS_META_DEFAULT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ret = regmap_field_write(meta_ctl->dptx_index, LPASS_META_DEFAULT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ret = regmap_field_write(sstream_ctl->dma_sel, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ret = regmap_field_write(sstream_ctl->auto_bbit_en, LPASS_SSTREAM_DEFAULT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ret = regmap_field_write(sstream_ctl->layout, LPASS_SSTREAM_DEFAULT_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ret = regmap_field_write(sstream_ctl->layout_sp, LPASS_LAYOUT_SP_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ret = regmap_field_write(sstream_ctl->dp_audio, LPASS_SSTREAM_DEFAULT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ret = regmap_field_write(sstream_ctl->set_sp_on_en, LPASS_SSTREAM_DEFAULT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ret = regmap_field_write(sstream_ctl->dp_sp_b_hw_en, LPASS_SSTREAM_DEFAULT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ret = regmap_field_write(sstream_ctl->dp_staffing_en, LPASS_SSTREAM_DEFAULT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int lpass_hdmi_daiops_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ret = regmap_field_write(drvdata->sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ret = regmap_field_write(drvdata->meta_ctl->mute, LPASS_MUTE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int lpass_hdmi_daiops_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		ret = regmap_field_write(sstream_ctl->dp_audio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const struct snd_soc_dai_ops asoc_qcom_lpass_hdmi_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.hw_params	= lpass_hdmi_daiops_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.prepare	= lpass_hdmi_daiops_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.trigger	= lpass_hdmi_daiops_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) EXPORT_SYMBOL_GPL(asoc_qcom_lpass_hdmi_dai_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_DESCRIPTION("QTi LPASS HDMI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MODULE_LICENSE("GPL v2");