^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "lpass-lpaif-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "lpass.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPASS_CPU_MAX_MI2S_LINES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPASS_CPU_I2S_SD0_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LPASS_CPU_I2S_SD1_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPASS_CPU_I2S_SD2_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPASS_CPU_I2S_SD3_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct lpaif_i2sctl *i2sctl, struct regmap *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct lpass_data *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) IS_ERR(i2sctl->bitwidth))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int id = dai->driver->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Ensure LRCLK is disabled even in device node validation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Will not impact if disabled in lpass_cpu_daiops_trigger()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * BCLK may not be enabled if lpass_cpu_daiops_prepare is called before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * lpass_cpu_daiops_shutdown. It's paired with the clk_enable in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * lpass_cpu_daiops_prepare.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (drvdata->mi2s_was_prepared[dai->driver->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) drvdata->mi2s_was_prepared[dai->driver->id] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int id = dai->driver->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) snd_pcm_format_t format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int bitwidth, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bitwidth = snd_pcm_format_width(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (bitwidth < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return bitwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = regmap_fields_write(i2sctl->loopback, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) LPAIF_I2SCTL_LOOPBACK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(dai->dev, "error updating loopback field: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = regmap_fields_write(i2sctl->wssrc, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) LPAIF_I2SCTL_WSSRC_INTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) switch (bitwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) regval = LPAIF_I2SCTL_BITWIDTH_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) regval = LPAIF_I2SCTL_BITWIDTH_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) regval = LPAIF_I2SCTL_BITWIDTH_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mode = drvdata->mi2s_playback_sd_mode[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mode = drvdata->mi2s_capture_sd_mode[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err(dai->dev, "no line is assigned\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) switch (channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case LPAIF_I2SCTL_MODE_QUAD01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case LPAIF_I2SCTL_MODE_6CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case LPAIF_I2SCTL_MODE_8CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mode = LPAIF_I2SCTL_MODE_SD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case LPAIF_I2SCTL_MODE_QUAD23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mode = LPAIF_I2SCTL_MODE_SD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case LPAIF_I2SCTL_MODE_6CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case LPAIF_I2SCTL_MODE_8CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mode = LPAIF_I2SCTL_MODE_QUAD01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (mode < LPAIF_I2SCTL_MODE_6CH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case LPAIF_I2SCTL_MODE_8CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mode = LPAIF_I2SCTL_MODE_6CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (mode < LPAIF_I2SCTL_MODE_8CH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(dai->dev, "invalid channels given: %u\n", channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = regmap_fields_write(i2sctl->spkmode, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) LPAIF_I2SCTL_SPKMODE(mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (channels >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = regmap_fields_write(i2sctl->spkmono, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) LPAIF_I2SCTL_SPKMONO_STEREO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = regmap_fields_write(i2sctl->spkmono, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) LPAIF_I2SCTL_SPKMONO_MONO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = regmap_fields_write(i2sctl->micmode, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) LPAIF_I2SCTL_MICMODE(mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (channels >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = regmap_fields_write(i2sctl->micmono, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) LPAIF_I2SCTL_MICMONO_STEREO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = regmap_fields_write(i2sctl->micmono, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) LPAIF_I2SCTL_MICMONO_MONO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rate * bitwidth * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) rate * bitwidth * 2, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int id = dai->driver->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Ensure lpass BCLK/LRCLK is enabled during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * device resume as lpass_cpu_daiops_prepare() is not called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * after the device resumes. We don't check mi2s_was_prepared before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * enable/disable BCLK in trigger events because:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * 1. These trigger events are paired, so the BCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * enable_count is balanced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * 2. the BCLK can be shared (ex: headset and headset mic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * we need to increase the enable_count so that we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * turn off the shared BCLK while other devices are using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = regmap_fields_write(i2sctl->spken, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) LPAIF_I2SCTL_SPKEN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = regmap_fields_write(i2sctl->micen, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) LPAIF_I2SCTL_MICEN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = clk_enable(drvdata->mi2s_bit_clk[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) clk_disable(drvdata->mi2s_osr_clk[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * To ensure lpass BCLK/LRCLK is disabled during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * device suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = regmap_fields_write(i2sctl->spken, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) LPAIF_I2SCTL_SPKEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = regmap_fields_write(i2sctl->micen, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) LPAIF_I2SCTL_MICEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int id = dai->driver->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Ensure lpass BCLK/LRCLK is enabled bit before playback/capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * data flow starts. This allows other codec to have some delay before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * the data flow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * (ex: to drop start up pop noise before capture starts).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Check mi2s_was_prepared before enabling BCLK as lpass_cpu_daiops_prepare can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * be called multiple times. It's paired with the clk_disable in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * lpass_cpu_daiops_shutdown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!drvdata->mi2s_was_prepared[dai->driver->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = clk_enable(drvdata->mi2s_bit_clk[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) drvdata->mi2s_was_prepared[dai->driver->id] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .set_sysclk = lpass_cpu_daiops_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .startup = lpass_cpu_daiops_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .shutdown = lpass_cpu_daiops_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .hw_params = lpass_cpu_daiops_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .trigger = lpass_cpu_daiops_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .prepare = lpass_cpu_daiops_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* ensure audio hardware is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = regmap_write(drvdata->lpaif_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct of_phandle_args *args,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) const char **dai_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct lpass_variant *variant = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int id = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) for (i = 0; i < variant->num_dai; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (variant->dai_driver[i].id == id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *dai_name = variant->dai_driver[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = "lpass-cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .of_xlate_dai_name = asoc_qcom_of_xlate_dai_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct lpass_data *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (i = 0; i < v->i2s_ports; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (reg == LPAIF_I2SCTL_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (i = 0; i < v->irq_ports; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (reg == LPAIF_IRQEN_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (reg == LPAIF_IRQCLEAR_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (i = 0; i < v->rdma_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (reg == LPAIF_RDMACTL_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (reg == LPAIF_RDMABASE_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (reg == LPAIF_RDMABUFF_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (reg == LPAIF_RDMAPER_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) for (i = 0; i < v->wrdma_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct lpass_data *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (i = 0; i < v->i2s_ports; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (reg == LPAIF_I2SCTL_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for (i = 0; i < v->irq_ports; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (reg == LPAIF_IRQEN_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (reg == LPAIF_IRQSTAT_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (i = 0; i < v->rdma_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (reg == LPAIF_RDMACTL_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (reg == LPAIF_RDMABASE_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (reg == LPAIF_RDMABUFF_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (reg == LPAIF_RDMACURR_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (reg == LPAIF_RDMAPER_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) for (i = 0; i < v->wrdma_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct lpass_data *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) for (i = 0; i < v->irq_ports; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (reg == LPAIF_IRQSTAT_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) for (i = 0; i < v->rdma_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (reg == LPAIF_RDMACURR_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) for (i = 0; i < v->wrdma_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct regmap_config lpass_cpu_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .writeable_reg = lpass_cpu_regmap_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .readable_reg = lpass_cpu_regmap_readable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .volatile_reg = lpass_cpu_regmap_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct lpass_data *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct lpass_hdmi_tx_ctl *tx_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct regmap_field *legacy_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct lpass_vbit_ctrl *vbit_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct regmap_field *tx_parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct lpass_dp_metadata_ctl *meta_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct lpass_sstream_ctl *sstream_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct regmap_field *ch_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct regmap_field *ch_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct lpass_hdmitx_dmactl *tx_dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!tx_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) drvdata->tx_ctl = tx_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) drvdata->hdmitx_legacy_en = legacy_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!vbit_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) drvdata->vbit_ctl = vbit_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) drvdata->hdmitx_parity_calc_en = tx_parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (!meta_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) drvdata->meta_ctl = meta_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!sstream_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) drvdata->sstream_ctl = sstream_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) drvdata->hdmitx_ch_msb[i] = ch_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) drvdata->hdmitx_ch_lsb[i] = ch_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!tx_dmactl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct lpass_data *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (reg == LPASS_HDMI_TX_DP_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for (i = 0; i < v->hdmi_rdma_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (i = 0; i < v->hdmi_rdma_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct lpass_data *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) for (i = 0; i < v->hdmi_rdma_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (reg == LPASS_HDMI_TX_DP_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) for (i = 0; i < v->hdmi_rdma_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct lpass_data *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) for (i = 0; i < v->hdmi_rdma_channels; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct regmap_config lpass_hdmi_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .writeable_reg = lpass_hdmi_regmap_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .readable_reg = lpass_hdmi_regmap_readable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .volatile_reg = lpass_hdmi_regmap_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) unsigned int sd_line_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int num_lines, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) LPASS_CPU_MAX_MI2S_LINES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (num_lines < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return LPAIF_I2SCTL_MODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) for (i = 0; i < num_lines; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) sd_line_mask |= BIT(lines[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) switch (sd_line_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case LPASS_CPU_I2S_SD0_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return LPAIF_I2SCTL_MODE_SD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case LPASS_CPU_I2S_SD1_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return LPAIF_I2SCTL_MODE_SD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case LPASS_CPU_I2S_SD2_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return LPAIF_I2SCTL_MODE_SD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case LPASS_CPU_I2S_SD3_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return LPAIF_I2SCTL_MODE_SD3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case LPASS_CPU_I2S_SD0_1_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return LPAIF_I2SCTL_MODE_QUAD01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case LPASS_CPU_I2S_SD2_3_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return LPAIF_I2SCTL_MODE_QUAD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case LPASS_CPU_I2S_SD0_1_2_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return LPAIF_I2SCTL_MODE_6CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case LPASS_CPU_I2S_SD0_1_2_3_MASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return LPAIF_I2SCTL_MODE_8CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return LPAIF_I2SCTL_MODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static void of_lpass_cpu_parse_dai_data(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct lpass_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int ret, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Allow all channels by default for backwards compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) for (id = 0; id < data->variant->num_dai; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) for_each_child_of_node(dev->of_node, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = of_property_read_u32(node, "reg", &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (ret || id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev_err(dev, "valid dai id not found: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (id == LPASS_DP_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) data->hdmi_port_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) data->mi2s_playback_sd_mode[id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) of_lpass_cpu_parse_sd_lines(dev, node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "qcom,playback-sd-lines");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) data->mi2s_capture_sd_mode[id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) of_lpass_cpu_parse_sd_lines(dev, node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "qcom,capture-sd-lines");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct lpass_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct device_node *dsp_of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct lpass_variant *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int ret, i, dai_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (dsp_of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_err(dev, "DSP exists and holds audio resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) platform_set_drvdata(pdev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) match = of_match_device(dev->driver->of_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) drvdata->variant = (struct lpass_variant *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) variant = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) of_lpass_cpu_parse_dai_data(dev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) drvdata->lpaif = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (IS_ERR((void const __force *)drvdata->lpaif)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev_err(dev, "error mapping reg resource: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PTR_ERR((void const __force *)drvdata->lpaif));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return PTR_ERR((void const __force *)drvdata->lpaif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) variant->wrdma_channels +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) variant->wrdma_channel_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) &lpass_cpu_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (IS_ERR(drvdata->lpaif_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dev_err(dev, "error initializing regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PTR_ERR(drvdata->lpaif_map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return PTR_ERR(drvdata->lpaif_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (drvdata->hdmi_port_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-hdmiif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) drvdata->hdmiif = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (IS_ERR((void const __force *)drvdata->hdmiif)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_err(dev, "error mapping reg resource: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PTR_ERR((void const __force *)drvdata->hdmiif));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return PTR_ERR((void const __force *)drvdata->hdmiif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) variant->hdmi_rdma_channels - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) &lpass_hdmi_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (IS_ERR(drvdata->hdmiif_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev_err(dev, "error initializing regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PTR_ERR(drvdata->hdmiif_map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return PTR_ERR(drvdata->hdmiif_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (variant->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ret = variant->init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_err(dev, "error initializing variant: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) for (i = 0; i < variant->num_dai; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dai_id = variant->dai_driver[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (dai_id == LPASS_DP_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) variant->dai_osr_clk_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) variant->dai_bit_clk_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "error getting %s: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) variant->dai_bit_clk_names[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Allocation for i2sctl regmap fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* Initialize bitfields for dai I2SCTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) drvdata->lpaif_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dev_err(dev, "error init i2sctl field: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (drvdata->hdmi_port_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(dev, "%s error hdmi init failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = devm_snd_soc_register_component(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) &lpass_cpu_comp_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) variant->dai_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) variant->num_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dev_err(dev, "error registering cpu driver: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret = asoc_qcom_lpass_platform_register(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_err(dev, "error registering platform driver: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct lpass_data *drvdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (drvdata->variant->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) drvdata->variant->exit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) MODULE_DESCRIPTION("QTi LPASS CPU Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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