^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * lpass-apq8016.c -- ALSA SoC CPU DAI driver for APQ8016 LPASS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <dt-bindings/sound/apq8016-lpass.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "lpass-lpaif-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "lpass.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct snd_soc_dai_driver apq8016_lpass_cpu_dai_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [MI2S_PRIMARY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .id = MI2S_PRIMARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .name = "Primary MI2S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .stream_name = "Primary Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .formats = SNDRV_PCM_FMTBIT_S16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SNDRV_PCM_FMTBIT_S24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SNDRV_PCM_FMTBIT_S32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .rates = SNDRV_PCM_RATE_8000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SNDRV_PCM_RATE_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .probe = &asoc_qcom_lpass_cpu_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .ops = &asoc_qcom_lpass_cpu_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [MI2S_SECONDARY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .id = MI2S_SECONDARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "Secondary MI2S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .stream_name = "Secondary Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .formats = SNDRV_PCM_FMTBIT_S16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SNDRV_PCM_FMTBIT_S24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SNDRV_PCM_FMTBIT_S32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .rates = SNDRV_PCM_RATE_8000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SNDRV_PCM_RATE_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .probe = &asoc_qcom_lpass_cpu_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .ops = &asoc_qcom_lpass_cpu_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [MI2S_TERTIARY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .id = MI2S_TERTIARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .name = "Tertiary MI2S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .stream_name = "Tertiary Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .formats = SNDRV_PCM_FMTBIT_S16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SNDRV_PCM_FMTBIT_S24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SNDRV_PCM_FMTBIT_S32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .rates = SNDRV_PCM_RATE_8000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SNDRV_PCM_RATE_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .probe = &asoc_qcom_lpass_cpu_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .ops = &asoc_qcom_lpass_cpu_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [MI2S_QUATERNARY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .id = MI2S_QUATERNARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "Quatenary MI2S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .stream_name = "Quatenary Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .formats = SNDRV_PCM_FMTBIT_S16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SNDRV_PCM_FMTBIT_S24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SNDRV_PCM_FMTBIT_S32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .rates = SNDRV_PCM_RATE_8000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SNDRV_PCM_RATE_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .stream_name = "Quatenary Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .formats = SNDRV_PCM_FMTBIT_S16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SNDRV_PCM_FMTBIT_S24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SNDRV_PCM_FMTBIT_S32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .rates = SNDRV_PCM_RATE_8000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SNDRV_PCM_RATE_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .rate_max = 96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .probe = &asoc_qcom_lpass_cpu_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .ops = &asoc_qcom_lpass_cpu_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int apq8016_lpass_alloc_dma_channel(struct lpass_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int direction, unsigned int dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct lpass_variant *v = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) v->rdma_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (chan >= v->rdma_channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) v->wrdma_channel_start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) v->wrdma_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) v->wrdma_channel_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (chan >= v->wrdma_channel_start + v->wrdma_channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) set_bit(chan, &drvdata->dma_ch_bit_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int apq8016_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clear_bit(chan, &drvdata->dma_ch_bit_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int apq8016_lpass_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct lpass_data *drvdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct lpass_variant *variant = drvdata->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) drvdata->clks = devm_kcalloc(dev, variant->num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sizeof(*drvdata->clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!drvdata->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) drvdata->num_clks = variant->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) for (i = 0; i < drvdata->num_clks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) drvdata->clks[i].id = variant->clk_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(dev, "Failed to get clocks %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_err(dev, "apq8016 clk_enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) drvdata->ahbix_clk = devm_clk_get(dev, "ahbix-clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (IS_ERR(drvdata->ahbix_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(dev, "error getting ahbix-clk: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PTR_ERR(drvdata->ahbix_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = PTR_ERR(drvdata->ahbix_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto err_ahbix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(dev, "error setting rate on ahbix_clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto err_ahbix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_dbg(dev, "set ahbix_clk rate to %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clk_get_rate(drvdata->ahbix_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = clk_prepare_enable(drvdata->ahbix_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(dev, "error enabling ahbix_clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) goto err_ahbix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) err_ahbix_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int apq8016_lpass_exit(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct lpass_data *drvdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) clk_disable_unprepare(drvdata->ahbix_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct lpass_variant apq8016_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .i2sctrl_reg_base = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .i2sctrl_reg_stride = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .i2s_ports = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .irq_reg_base = 0x6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .irq_reg_stride = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .irq_ports = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .rdma_reg_base = 0x8400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .rdma_reg_stride = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .rdma_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .dmactl_audif_start = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .wrdma_reg_base = 0xB000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .wrdma_reg_stride = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .wrdma_channel_start = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .wrdma_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .loopback = REG_FIELD_ID(0x1000, 15, 15, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .spken = REG_FIELD_ID(0x1000, 14, 14, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .spkmode = REG_FIELD_ID(0x1000, 10, 13, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .spkmono = REG_FIELD_ID(0x1000, 9, 9, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .micen = REG_FIELD_ID(0x1000, 8, 8, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .micmode = REG_FIELD_ID(0x1000, 4, 7, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .micmono = REG_FIELD_ID(0x1000, 3, 3, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .wssrc = REG_FIELD_ID(0x1000, 2, 2, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 4, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .rdma_dyncclk = REG_FIELD_ID(0x8400, 12, 12, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .rdma_bursten = REG_FIELD_ID(0x8400, 11, 11, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .rdma_wpscnt = REG_FIELD_ID(0x8400, 8, 10, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .rdma_intf = REG_FIELD_ID(0x8400, 4, 7, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .rdma_fifowm = REG_FIELD_ID(0x8400, 1, 3, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .rdma_enable = REG_FIELD_ID(0x8400, 0, 0, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .wrdma_dyncclk = REG_FIELD_ID(0xB000, 12, 12, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .wrdma_bursten = REG_FIELD_ID(0xB000, 11, 11, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .wrdma_wpscnt = REG_FIELD_ID(0xB000, 8, 10, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .wrdma_intf = REG_FIELD_ID(0xB000, 4, 7, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .wrdma_fifowm = REG_FIELD_ID(0xB000, 1, 3, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .wrdma_enable = REG_FIELD_ID(0xB000, 0, 0, 2, 0x1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .clk_name = (const char*[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "pcnoc-mport-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "pcnoc-sway-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .num_clks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .dai_driver = apq8016_lpass_cpu_dai_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .num_dai = ARRAY_SIZE(apq8016_lpass_cpu_dai_driver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .dai_osr_clk_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "mi2s-osr-clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "mi2s-osr-clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "mi2s-osr-clk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "mi2s-osr-clk3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .dai_bit_clk_names = (const char *[]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "mi2s-bit-clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "mi2s-bit-clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "mi2s-bit-clk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "mi2s-bit-clk3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .init = apq8016_lpass_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .exit = apq8016_lpass_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .alloc_dma_channel = apq8016_lpass_alloc_dma_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .free_dma_channel = apq8016_lpass_free_dma_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct of_device_id apq8016_lpass_cpu_device_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { .compatible = "qcom,lpass-cpu-apq8016", .data = &apq8016_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_DEVICE_TABLE(of, apq8016_lpass_cpu_device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct platform_driver apq8016_lpass_cpu_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .name = "apq8016-lpass-cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .of_match_table = of_match_ptr(apq8016_lpass_cpu_device_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .probe = asoc_qcom_lpass_cpu_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .remove = asoc_qcom_lpass_cpu_platform_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) module_platform_driver(apq8016_lpass_cpu_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MODULE_DESCRIPTION("APQ8016 LPASS CPU Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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