^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2018, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <sound/soc-dapm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SLIM_MAX_TX_PORTS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SLIM_MAX_RX_PORTS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define WCD9335_DEFAULT_MCLK_RATE 9600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static int apq8096_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct snd_interval *rate = hw_param_interval(params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) SNDRV_PCM_HW_PARAM_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct snd_interval *channels = hw_param_interval(params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SNDRV_PCM_HW_PARAM_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) rate->min = rate->max = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) channels->min = channels->max = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int msm_snd_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ret = snd_soc_dai_get_channel_map(codec_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (ret != 0 && ret != -ENOTSUPP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pr_err("failed to get codec chan map, err:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) } else if (ret == -ENOTSUPP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) rx_ch_cnt, rx_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret = snd_soc_dai_set_channel_map(cpu_dai, tx_ch_cnt, tx_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ret != 0 && ret != -ENOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pr_err("Failed to set cpu chan map, err:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) else if (ret == -ENOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct snd_soc_ops apq8096_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .hw_params = msm_snd_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int apq8096_init(struct snd_soc_pcm_runtime *rtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Codec SLIMBUS configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * TX14, TX15, TX16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int rx_ch[SLIM_MAX_RX_PORTS] = {144, 145, 146, 147, 148, 149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 150, 151, 152, 153, 154, 155, 156};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int tx_ch[SLIM_MAX_TX_PORTS] = {128, 129, 130, 131, 132, 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 134, 135, 136, 137, 138, 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 140, 141, 142, 143};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) snd_soc_dai_set_sysclk(codec_dai, 0, WCD9335_DEFAULT_MCLK_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void apq8096_add_be_ops(struct snd_soc_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct snd_soc_dai_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) for_each_card_prelinks(card, i, link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (link->no_pcm == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) link->be_hw_params_fixup = apq8096_be_hw_params_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) link->init = apq8096_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) link->ops = &apq8096_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int apq8096_platform_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct snd_soc_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) card->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) card->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_set_drvdata(dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = qcom_snd_parse_of(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) apq8096_add_be_ops(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return devm_snd_soc_register_card(dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct of_device_id msm_snd_apq8096_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {.compatible = "qcom,apq8096-sndcard"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MODULE_DEVICE_TABLE(of, msm_snd_apq8096_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct platform_driver msm_snd_apq8096_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .probe = apq8096_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "msm-snd-apq8096",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .of_match_table = msm_snd_apq8096_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) module_platform_driver(msm_snd_apq8096_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MODULE_DESCRIPTION("APQ8096 ASoC Machine Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODULE_LICENSE("GPL v2");