^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pxa2xx-i2s.c -- ALSA Soc Audio Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Liam Girdwood
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * lrg@slimlogic.co.uk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/pxa2xx-lib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <mach/audio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "pxa2xx-i2s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * I2S Controller Register and Bit Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SACR0 __REG(0x40400000) /* Global Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SACR0_ENB (1 << 0) /* Enable I2S Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SACR1_ENLBF (1 << 5) /* Enable Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SACR1_DREC (1 << 3) /* Disable Recording Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SASR0_I2SOFF (1 << 7) /* Controller Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SASR0_BSY (1 << 2) /* I2S Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct pxa_i2s_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 sadiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 sacr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 sacr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 saimr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static struct pxa_i2s_port pxa_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct clk *clk_i2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int clk_ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .addr = __PREG(SADR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .chan_name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .maxburst = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_in = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .addr = __PREG(SADR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .chan_name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .maxburst = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (IS_ERR(clk_i2s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return PTR_ERR(clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!snd_soc_dai_active(cpu_dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SACR0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* wait for I2S controller to be ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int pxa_i2s_wait(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* flush the Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SADR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* interface format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pxa_i2s.fmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pxa_i2s.fmt = SACR1_AMSL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pxa_i2s.master = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pxa_i2s.master = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (clk_id != PXA2XX_I2S_SYSCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (WARN_ON(IS_ERR(clk_i2s)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_prepare_enable(clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clk_ena = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pxa_i2s_wait();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dma_data = &pxa2xx_i2s_pcm_stereo_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dma_data = &pxa2xx_i2s_pcm_stereo_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) snd_soc_dai_set_dma_data(dai, substream, dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* is port used by another stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!(SACR0 & SACR0_ENB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SACR0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (pxa_i2s.master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SACR0 |= SACR0_BCKD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SACR1 |= pxa_i2s.fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SAIMR |= SAIMR_TFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SAIMR |= SAIMR_RFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) switch (params_rate(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SADIV = 0x48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SADIV = 0x34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) SADIV = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SADIV = 0x1a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SADIV = 0xd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SADIV = 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case 96000: /* not in manual and possibly slightly inaccurate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SADIV = 0x6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SACR1 &= ~SACR1_DRPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SACR1 &= ~SACR1_DREC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SACR0 |= SACR0_ENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SACR1 |= SACR1_DRPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) SAIMR &= ~SAIMR_TFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SACR1 |= SACR1_DREC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SAIMR &= ~SAIMR_RFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if ((SACR1 & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SACR0 &= ~SACR0_ENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pxa_i2s_wait();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (clk_ena) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clk_disable_unprepare(clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) clk_ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int pxa2xx_soc_pcm_suspend(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* store registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pxa_i2s.sacr0 = SACR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pxa_i2s.sacr1 = SACR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pxa_i2s.saimr = SAIMR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pxa_i2s.sadiv = SADIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* deactivate link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SACR0 &= ~SACR0_ENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pxa_i2s_wait();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int pxa2xx_soc_pcm_resume(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pxa_i2s_wait();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SACR1 = pxa_i2s.sacr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SAIMR = pxa_i2s.saimr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SADIV = pxa_i2s.sadiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SACR0 = pxa_i2s.sacr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define pxa2xx_soc_pcm_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define pxa2xx_soc_pcm_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int pxa2xx_i2s_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk_i2s = clk_get(dai->dev, "I2SCLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (IS_ERR(clk_i2s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return PTR_ERR(clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * PXA Developer's Manual:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * If SACR0[ENB] is toggled in the middle of a normal operation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * the SACR0[RST] bit must also be set and cleared to reset all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * I2S controller registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SACR0 = SACR0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SACR0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Make sure RPL and REC are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SACR1 = SACR1_DRPL | SACR1_DREC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Along with FIFO servicing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SAIMR &= ~(SAIMR_RFS | SAIMR_TFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) snd_soc_dai_init_dma_data(dai, &pxa2xx_i2s_pcm_stereo_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) &pxa2xx_i2s_pcm_stereo_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int pxa2xx_i2s_remove(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk_put(clk_i2s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clk_i2s = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct snd_soc_dai_ops pxa_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .startup = pxa2xx_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .shutdown = pxa2xx_i2s_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .trigger = pxa2xx_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .hw_params = pxa2xx_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .set_fmt = pxa2xx_i2s_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct snd_soc_dai_driver pxa_i2s_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .probe = pxa2xx_i2s_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .remove = pxa2xx_i2s_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .rates = PXA2XX_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .formats = SNDRV_PCM_FMTBIT_S16_LE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .rates = PXA2XX_I2S_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .formats = SNDRV_PCM_FMTBIT_S16_LE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .ops = &pxa_i2s_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct snd_soc_component_driver pxa_i2s_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .name = "pxa-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .pcm_construct = pxa2xx_soc_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .pcm_destruct = pxa2xx_soc_pcm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .open = pxa2xx_soc_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .close = pxa2xx_soc_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .hw_params = pxa2xx_soc_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .hw_free = pxa2xx_soc_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .prepare = pxa2xx_soc_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .trigger = pxa2xx_soc_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .pointer = pxa2xx_soc_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .mmap = pxa2xx_soc_pcm_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .suspend = pxa2xx_soc_pcm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .resume = pxa2xx_soc_pcm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int pxa2xx_i2s_drv_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return devm_snd_soc_register_component(&pdev->dev, &pxa_i2s_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) &pxa_i2s_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct platform_driver pxa2xx_i2s_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .probe = pxa2xx_i2s_drv_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "pxa2xx-i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int __init pxa2xx_i2s_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk_i2s = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return platform_driver_register(&pxa2xx_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void __exit pxa2xx_i2s_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) platform_driver_unregister(&pxa2xx_i2s_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) module_init(pxa2xx_i2s_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) module_exit(pxa2xx_i2s_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MODULE_ALIAS("platform:pxa2xx-i2s");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags