Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author:	Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Created:	Dec 02, 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright:	MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/dma/pxa-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/ac97/controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/pxa2xx-lib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <mach/regs-ac97.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <mach/audio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static void pxa2xx_ac97_warm_reset(struct ac97_controller *adrv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	pxa2xx_ac97_try_warm_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	pxa2xx_ac97_finish_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static void pxa2xx_ac97_cold_reset(struct ac97_controller *adrv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	pxa2xx_ac97_try_cold_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	pxa2xx_ac97_finish_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static int pxa2xx_ac97_read_actrl(struct ac97_controller *adrv, int slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 				  unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return pxa2xx_ac97_read(slot, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int pxa2xx_ac97_write_actrl(struct ac97_controller *adrv, int slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 				   unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return pxa2xx_ac97_write(slot, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static struct ac97_controller_ops pxa2xx_ac97_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.read	= pxa2xx_ac97_read_actrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.write	= pxa2xx_ac97_write_actrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.warm_reset	= pxa2xx_ac97_warm_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.reset	= pxa2xx_ac97_cold_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_in = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.addr		= __PREG(PCDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.addr_width	= DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.chan_name	= "pcm_pcm_stereo_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.maxburst	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_stereo_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.addr		= __PREG(PCDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.addr_width	= DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.chan_name	= "pcm_pcm_stereo_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.maxburst	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.addr		= __PREG(MODR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.addr_width	= DMA_SLAVE_BUSWIDTH_2_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.chan_name	= "pcm_aux_mono_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.maxburst	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_aux_mono_in = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.addr		= __PREG(MODR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.addr_width	= DMA_SLAVE_BUSWIDTH_2_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.chan_name	= "pcm_aux_mono_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.maxburst	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static struct snd_dmaengine_dai_dma_data pxa2xx_ac97_pcm_mic_mono_in = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.addr		= __PREG(MCDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.addr_width	= DMA_SLAVE_BUSWIDTH_2_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.chan_name	= "pcm_aux_mic_mono",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.maxburst	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static int pxa2xx_ac97_hifi_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				    struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		dma_data = &pxa2xx_ac97_pcm_stereo_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		dma_data = &pxa2xx_ac97_pcm_stereo_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int pxa2xx_ac97_aux_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				   struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		dma_data = &pxa2xx_ac97_pcm_aux_mono_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		dma_data = &pxa2xx_ac97_pcm_aux_mono_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int pxa2xx_ac97_mic_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				   struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	snd_soc_dai_set_dma_data(cpu_dai, substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				 &pxa2xx_ac97_pcm_mic_mono_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		SNDRV_PCM_RATE_48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct snd_soc_dai_ops pxa_ac97_hifi_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.startup	= pxa2xx_ac97_hifi_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct snd_soc_dai_ops pxa_ac97_aux_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.startup	= pxa2xx_ac97_aux_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct snd_soc_dai_ops pxa_ac97_mic_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.startup	= pxa2xx_ac97_mic_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * There is only 1 physical AC97 interface for pxa2xx, but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * has extra fifo's that can be used for aux DACs and ADCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct snd_soc_dai_driver pxa_ac97_dai_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.name = "pxa2xx-ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.stream_name = "AC97 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.rates = PXA2XX_AC97_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.stream_name = "AC97 Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.rates = PXA2XX_AC97_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.ops = &pxa_ac97_hifi_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.name = "pxa2xx-ac97-aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.stream_name = "AC97 Aux Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.rates = PXA2XX_AC97_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.stream_name = "AC97 Aux Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.rates = PXA2XX_AC97_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.ops = &pxa_ac97_aux_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.name = "pxa2xx-ac97-mic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.stream_name = "AC97 Mic Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.rates = PXA2XX_AC97_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.ops = &pxa_ac97_mic_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct snd_soc_component_driver pxa_ac97_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.name		= "pxa-ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.pcm_construct	= pxa2xx_soc_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.pcm_destruct	= pxa2xx_soc_pcm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.open		= pxa2xx_soc_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.close		= pxa2xx_soc_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.hw_params	= pxa2xx_soc_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.hw_free	= pxa2xx_soc_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.prepare	= pxa2xx_soc_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.trigger	= pxa2xx_soc_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.pointer	= pxa2xx_soc_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.mmap		= pxa2xx_soc_pcm_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct of_device_id pxa2xx_ac97_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	{ .compatible = "marvell,pxa250-ac97", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	{ .compatible = "marvell,pxa270-ac97", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	{ .compatible = "marvell,pxa300-ac97", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_DEVICE_TABLE(of, pxa2xx_ac97_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int pxa2xx_ac97_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct ac97_controller *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	pxa2xx_audio_ops_t *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	void **codecs_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (pdev->id != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		dev_err(&pdev->dev, "PXA2xx has only one AC97 port.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	ret = pxa2xx_ac97_hw_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_err(&pdev->dev, "PXA2xx AC97 hw probe error (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	codecs_pdata = pdata ? pdata->codec_pdata : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ctrl = snd_ac97_controller_register(&pxa2xx_ac97_ops, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 					    AC97_SLOTS_AVAILABLE_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					    codecs_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (IS_ERR(ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return PTR_ERR(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	platform_set_drvdata(pdev, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	/* Punt most of the init to the SoC probe; we may need the machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 * driver to do interesting things with the clocking to get us up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * and running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return devm_snd_soc_register_component(&pdev->dev, &pxa_ac97_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 					  pxa_ac97_dai_driver, ARRAY_SIZE(pxa_ac97_dai_driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int pxa2xx_ac97_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct ac97_controller *ctrl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	snd_ac97_controller_unregister(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	pxa2xx_ac97_hw_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int pxa2xx_ac97_dev_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	return pxa2xx_ac97_hw_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int pxa2xx_ac97_dev_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return pxa2xx_ac97_hw_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static SIMPLE_DEV_PM_OPS(pxa2xx_ac97_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		pxa2xx_ac97_dev_suspend, pxa2xx_ac97_dev_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct platform_driver pxa2xx_ac97_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.probe		= pxa2xx_ac97_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.remove		= pxa2xx_ac97_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.name	= "pxa2xx-ac97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.pm	= &pxa2xx_ac97_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.of_match_table = of_match_ptr(pxa2xx_ac97_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) module_platform_driver(pxa2xx_ac97_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_AUTHOR("Nicolas Pitre");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_ALIAS("platform:pxa2xx-ac97");