Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * ASoC PXA SSP port support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _PXA_SSP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _PXA_SSP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* SSP clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PXA_SSP_CLK_PLL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PXA_SSP_CLK_EXT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PXA_SSP_CLK_NET	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PXA_SSP_CLK_AUDIO	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PXA_SSP_CLK_NET_PLL	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* SSP audio dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PXA_SSP_AUDIO_DIV_ACDS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PXA_SSP_AUDIO_DIV_SCDB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PXA_SSP_DIV_SCR				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* SSP ACDS audio dividers values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PXA_SSP_CLK_AUDIO_DIV_1		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PXA_SSP_CLK_AUDIO_DIV_2		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PXA_SSP_CLK_AUDIO_DIV_4		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PXA_SSP_CLK_AUDIO_DIV_8		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PXA_SSP_CLK_AUDIO_DIV_16	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PXA_SSP_CLK_AUDIO_DIV_32	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* SSP divider bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PXA_SSP_CLK_SCDB_4		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PXA_SSP_CLK_SCDB_1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PXA_SSP_CLK_SCDB_8		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PXA_SSP_PLL_OUT  0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif