^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pxa-ssp.c -- ALSA Soc Audio Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005,2008 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Liam Girdwood
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * o Test network mode for > 16bit sample size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pxa2xx_ssp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <sound/pxa2xx-lib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "pxa-ssp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * SSP audio private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ssp_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct ssp_device *ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk *extclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long ssp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int dai_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int configured_dai_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) uint32_t cr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) uint32_t cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) uint32_t to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) uint32_t psp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void dump_registers(struct ssp_device *ssp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dev_dbg(ssp->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pxa_ssp_read_reg(ssp, SSTO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev_dbg(ssp->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pxa_ssp_read_reg(ssp, SSACD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void pxa_ssp_enable(struct ssp_device *ssp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) uint32_t sscr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __raw_writel(sscr0, ssp->mmio_base + SSCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void pxa_ssp_disable(struct ssp_device *ssp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) uint32_t sscr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __raw_writel(sscr0, ssp->mmio_base + SSCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int out, struct snd_dmaengine_dai_dma_data *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dma->maxburst = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dma->addr = ssp->phys_base + SSDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int pxa_ssp_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct snd_dmaengine_dai_dma_data *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!snd_soc_dai_active(cpu_dai)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clk_prepare_enable(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pxa_ssp_disable(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (priv->extclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clk_prepare_enable(priv->extclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "tx" : "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!snd_soc_dai_active(cpu_dai)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pxa_ssp_disable(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clk_disable_unprepare(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (priv->extclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk_disable_unprepare(priv->extclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int pxa_ssp_suspend(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!snd_soc_component_active(component))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk_prepare_enable(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) priv->to = __raw_readl(ssp->mmio_base + SSTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pxa_ssp_disable(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk_disable_unprepare(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int pxa_ssp_resume(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct ssp_priv *priv = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk_prepare_enable(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __raw_writel(sssr, ssp->mmio_base + SSSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __raw_writel(priv->to, ssp->mmio_base + SSTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (snd_soc_component_active(component))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pxa_ssp_enable(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clk_disable_unprepare(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define pxa_ssp_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define pxa_ssp_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * ssp_set_clkdiv - set SSP clock divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @div: serial clock rate divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ssp->type == PXA25x_SSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sscr0 &= ~0x0000ff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sscr0 &= ~0x000fff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sscr0 |= (div - 1) << 8; /* 1..4096 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pxa_ssp_write_reg(ssp, SSCR0, sscr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Set the SSP ports SYSCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (priv->extclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * For DT based boards, if an extclk is given, use it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * here and configure PXA_SSP_CLK_EXT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = clk_set_rate(priv->extclk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clk_id = PXA_SSP_CLK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_dbg(ssp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cpu_dai->id, clk_id, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case PXA_SSP_CLK_NET_PLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sscr0 |= SSCR0_MOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case PXA_SSP_CLK_PLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Internal PLL is fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ssp->type == PXA25x_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) priv->sysclk = 1843200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) priv->sysclk = 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case PXA_SSP_CLK_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) priv->sysclk = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sscr0 |= SSCR0_ECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case PXA_SSP_CLK_NET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) priv->sysclk = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) sscr0 |= SSCR0_NCS | SSCR0_MOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case PXA_SSP_CLK_AUDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) priv->sysclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pxa_ssp_set_scr(ssp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sscr0 |= SSCR0_ACS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* The SSP clock must be disabled when changing SSP clock mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * on PXA2xx. On PXA3xx it must be enabled when doing so. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ssp->type != PXA3xx_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) clk_disable_unprepare(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pxa_ssp_write_reg(ssp, SSCR0, sscr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ssp->type != PXA3xx_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) clk_prepare_enable(ssp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ssp->type == PXA3xx_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pxa_ssp_write_reg(ssp, SSACDD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case 5622000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case 11345000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ssacd |= (0x1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case 12235000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ssacd |= (0x2 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case 14857000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ssacd |= (0x3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case 32842000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ssacd |= (0x4 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case 48000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ssacd |= (0x5 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* PXA3xx has a clock ditherer which can be used to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * a wider range of frequencies - calculate a value for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ssp->type == PXA3xx_SSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u64 tmp = 19968;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tmp *= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) do_div(tmp, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val = (val << 16) | 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pxa_ssp_write_reg(ssp, SSACDD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ssacd |= (0x6 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_dbg(ssp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "Using SSACDD %x to supply %uHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) val, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pxa_ssp_write_reg(ssp, SSACD, ssacd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Set the active slots in TDM/Network mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 sscr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* set slot width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (slot_width > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) sscr0 |= SSCR0_DataSize(slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (slots > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* enable network mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) sscr0 |= SSCR0_MOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* set number of active slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sscr0 |= SSCR0_SlotsPerFrm(slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* set active slot mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pxa_ssp_write_reg(ssp, SSCR0, sscr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Tristate the SSP DAI lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int tristate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 sscr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (tristate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) sscr1 &= ~SSCR1_TTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) sscr1 |= SSCR1_TTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pxa_ssp_write_reg(ssp, SSCR1, sscr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Settings will be applied in hw_params() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) priv->dai_fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Set up the SSP DAI format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * The SSP Port must be inactive before calling this function as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * physical interface format is changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 sscr0, sscr1, sspsp, scfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* check if we need to change anything at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (priv->configured_dai_fmt == priv->dai_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* reset port settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ~(SSCR0_PSP | SSCR0_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ~(SSPSP_SFRMP | SSPSP_SCMODE(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sspsp |= SSPSP_SFRMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) sspsp |= SSPSP_SCMODE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sscr0 |= SSCR0_PSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* See hw_params() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) sspsp |= SSPSP_FSRT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) sscr0 |= SSCR0_MOD | SSCR0_PSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pxa_ssp_write_reg(ssp, SSCR0, sscr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pxa_ssp_write_reg(ssp, SSCR1, sscr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pxa_ssp_write_reg(ssp, SSPSP, sspsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pxa_ssp_write_reg(ssp, SSCR1, scfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dump_registers(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Since we are configuring the timings for the format by hand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * we have to defer some things until hw_params() where we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * know parameters like the sample size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) priv->configured_dai_fmt = priv->dai_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct pxa_ssp_clock_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 acds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 scdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Set the SSP audio DMA parameters and sample size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Can be called multiple times by oss emulation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int chn = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 sscr0, sspsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int width = snd_pcm_format_physical_width(params_format(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct snd_dmaengine_dai_dma_data *dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int bclk = rate * chn * (width / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Network mode with one active slot (ttsa == 1) can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * to force 16-bit frame width on the wire (for S16_LE), even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * with two channels. Use 16-bit DMA transfers for this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pxa_ssp_set_dma_params(ssp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ((chn == 2) && (ttsa != 1)) || (width == 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* we can only change the settings if the port is not in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = pxa_ssp_configure_dai_fmt(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* clear selected SSP bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* bit size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ssp->type == PXA3xx_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) sscr0 |= SSCR0_FPCKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) sscr0 |= SSCR0_DataSize(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pxa_ssp_write_reg(ssp, SSCR0, sscr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (sscr0 & SSCR0_ACS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = pxa_ssp_set_pll(priv, bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * If we were able to generate the bclk directly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * all is fine. Otherwise, look up the closest rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * from the table and also set the dividers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) const struct pxa_ssp_clock_mode *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int ssacd, acds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for (m = pxa_ssp_clock_modes; m->rate; m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (m->rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (!m->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) acds = m->acds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* The values in the table are for 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (width == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) acds--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = pxa_ssp_set_pll(priv, bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ssacd = pxa_ssp_read_reg(ssp, SSACD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ssacd |= SSACD_ACDS(m->acds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ssacd |= m->scdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pxa_ssp_write_reg(ssp, SSACD, ssacd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) } else if (sscr0 & SSCR0_ECS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * For setups with external clocking, the PLL and its diviers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * are not active. Instead, the SCR bits in SSCR0 can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * to divide the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) pxa_ssp_set_scr(ssp, bclk / rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) sspsp = pxa_ssp_read_reg(ssp, SSPSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (((priv->sysclk / bclk) == 64) && (width == 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* This is a special case where the bitclk is 64fs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * and we're not dealing with 2*32 bits of audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * samples.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * The SSP values used for that are all found out by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * trying and failing a lot; some of the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * needed for that mode are only available on PXA3xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ssp->type != PXA3xx_SSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) sspsp |= SSPSP_SFRMWDTH(width * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) sspsp |= SSPSP_SFRMDLY(width * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) sspsp |= SSPSP_EDMYSTOP(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) sspsp |= SSPSP_DMYSTOP(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) sspsp |= SSPSP_DMYSTRT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* The frame width is the width the LRCLK is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * asserted for; the delay is expressed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * half cycle units. We need the extra cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * because the data starts clocking out one BCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * after LRCLK changes polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) sspsp |= SSPSP_SFRMWDTH(width + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) sspsp |= SSPSP_DMYSTRT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pxa_ssp_write_reg(ssp, SSPSP, sspsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* When we use a network mode, we always require TDM slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * - complain loudly and fail if they've not been set up yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if ((sscr0 & SSCR0_MOD) && !ttsa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_err(ssp->dev, "No TDM timeslot configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dump_registers(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct ssp_device *ssp, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (value && (sscr0 & SSCR0_SSE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) sscr1 |= SSCR1_TSRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) sscr1 &= ~SSCR1_TSRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) sscr1 |= SSCR1_RSRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) sscr1 &= ~SSCR1_RSRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pxa_ssp_write_reg(ssp, SSCR1, sscr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pxa_ssp_write_reg(ssp, SSSR, sssr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pxa_ssp_write_reg(ssp, SSPSP, sspsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct ssp_device *ssp = priv->ssp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pxa_ssp_enable(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pxa_ssp_set_running_bit(substream, ssp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) val = pxa_ssp_read_reg(ssp, SSSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pxa_ssp_write_reg(ssp, SSSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pxa_ssp_set_running_bit(substream, ssp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) pxa_ssp_set_running_bit(substream, ssp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pxa_ssp_disable(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pxa_ssp_set_running_bit(substream, ssp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dump_registers(ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int pxa_ssp_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct device *dev = dai->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct ssp_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct device_node *ssp_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (!ssp_handle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_err(dev, "unable to get 'port' phandle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (priv->ssp == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) priv->extclk = devm_clk_get(dev, "extclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (IS_ERR(priv->extclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = PTR_ERR(priv->extclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) priv->extclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (priv->ssp == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) priv->dai_fmt = (unsigned int) -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) snd_soc_dai_set_drvdata(dai, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) err_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int pxa_ssp_remove(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) pxa_ssp_free(priv->ssp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .startup = pxa_ssp_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .shutdown = pxa_ssp_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .trigger = pxa_ssp_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .hw_params = pxa_ssp_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .set_sysclk = pxa_ssp_set_dai_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .set_fmt = pxa_ssp_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .set_tristate = pxa_ssp_set_dai_tristate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static struct snd_soc_dai_driver pxa_ssp_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .probe = pxa_ssp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .remove = pxa_ssp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .rates = PXA_SSP_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .formats = PXA_SSP_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .rates = PXA_SSP_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .formats = PXA_SSP_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .ops = &pxa_ssp_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const struct snd_soc_component_driver pxa_ssp_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .name = "pxa-ssp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .pcm_construct = pxa2xx_soc_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .pcm_destruct = pxa2xx_soc_pcm_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .open = pxa2xx_soc_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .close = pxa2xx_soc_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .hw_params = pxa2xx_soc_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .hw_free = pxa2xx_soc_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .prepare = pxa2xx_soc_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .trigger = pxa2xx_soc_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .pointer = pxa2xx_soc_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .mmap = pxa2xx_soc_pcm_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .suspend = pxa_ssp_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .resume = pxa_ssp_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const struct of_device_id pxa_ssp_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { .compatible = "mrvl,pxa-ssp-dai" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int asoc_ssp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &pxa_ssp_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static struct platform_driver asoc_ssp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .name = "pxa-ssp-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .of_match_table = of_match_ptr(pxa_ssp_of_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .probe = asoc_ssp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) module_platform_driver(asoc_ssp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MODULE_ALIAS("platform:pxa-ssp-dai");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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