Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * linux/sound/soc/pxa/mmp-sspa.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2011 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _MMP_SSPA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _MMP_SSPA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * SSPA Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SSPA_D			(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SSPA_ID			(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SSPA_CTL		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SSPA_SP			(0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SSPA_FIFO_UL		(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SSPA_INT_MASK		(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SSPA_C			(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SSPA_FIFO_NOFS		(0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SSPA_FIFO_SIZE		(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* SSPA Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define	SSPA_CTL_XPH		(1 << 31)	/* Read Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define	SSPA_CTL_XFIG		(1 << 15)	/* Transmit Zeros when FIFO Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define	SSPA_CTL_JST		(1 << 3)	/* Audio Sample Justification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define	SSPA_CTL_XFRLEN2_MASK	(7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define	SSPA_CTL_XFRLEN2(x)	((x) << 24)	/* Transmit Frame Length in Phase 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define	SSPA_CTL_XWDLEN2_MASK	(7 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define	SSPA_CTL_XWDLEN2(x)	((x) << 21)	/* Transmit Word Length in Phase 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define	SSPA_CTL_XDATDLY(x)	((x) << 19)	/* Transmit Data Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define	SSPA_CTL_XSSZ2_MASK	(7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define	SSPA_CTL_XSSZ2(x)	((x) << 16)	/* Transmit Sample Audio Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define	SSPA_CTL_XFRLEN1_MASK	(7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define	SSPA_CTL_XFRLEN1(x)	((x) << 8)	/* Transmit Frame Length in Phase 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define	SSPA_CTL_XWDLEN1_MASK	(7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define	SSPA_CTL_XWDLEN1(x)	((x) << 5)	/* Transmit Word Length in Phase 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define	SSPA_CTL_XSSZ1_MASK	(7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define	SSPA_CTL_XSSZ1(x)	((x) << 0)	/* XSSZ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SSPA_CTL_8_BITS		(0x0)		/* Sample Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SSPA_CTL_12_BITS	(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SSPA_CTL_16_BITS	(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SSPA_CTL_20_BITS	(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SSPA_CTL_24_BITS	(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SSPA_CTL_32_BITS	(0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* SSPA Serial Port Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define	SSPA_SP_WEN		(1 << 31)	/* Write Configuration Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define	SSPA_SP_MSL		(1 << 18)	/* Master Slave Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define	SSPA_SP_CLKP		(1 << 17)	/* CLKP Polarity Clock Edge Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define	SSPA_SP_FSP		(1 << 16)	/* FSP Polarity Clock Edge Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define	SSPA_SP_FFLUSH		(1 << 2)	/* FIFO Flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define	SSPA_SP_S_RST		(1 << 1)	/* Active High Reset Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define	SSPA_SP_S_EN		(1 << 0)	/* Serial Clock Domain Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define	SSPA_SP_FWID_MASK	(0x3f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define	SSPA_SP_FWID(x)		((x) << 20)	/* Frame-Sync Width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define	SSPA_TXSP_FPER_MASK	(0x3f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define	SSPA_TXSP_FPER(x)	((x) << 4)	/* Frame-Sync Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* sspa clock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MMP_SSPA_CLK_PLL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MMP_SSPA_CLK_VCXO	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MMP_SSPA_CLK_AUDIO	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* sspa pll id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MMP_SYSCLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MMP_SSPA_CLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif /* _MMP_SSPA_H */