Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/sound/soc/pxa/mmp-sspa.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Base on pxa2xx-ssp.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2011 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <sound/pxa2xx-lib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <sound/dmaengine_pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "mmp-sspa.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * SSPA audio private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct sspa_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	void __iomem *tx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	void __iomem *rx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct snd_dmaengine_dai_dma_data playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct snd_dmaengine_dai_dma_data capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct clk *audio_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct clk *sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	int running_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32 sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void mmp_sspa_tx_enable(struct sspa_priv *sspa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int sspa_sp = sspa->sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	sspa_sp &= ~SSPA_SP_MSL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	sspa_sp |= SSPA_SP_S_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	sspa_sp |= SSPA_SP_WEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void mmp_sspa_tx_disable(struct sspa_priv *sspa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned int sspa_sp = sspa->sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	sspa_sp &= ~SSPA_SP_MSL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	sspa_sp &= ~SSPA_SP_S_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	sspa_sp |= SSPA_SP_WEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	__raw_writel(sspa_sp, sspa->tx_base + SSPA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static void mmp_sspa_rx_enable(struct sspa_priv *sspa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned int sspa_sp = sspa->sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	sspa_sp |= SSPA_SP_S_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	sspa_sp |= SSPA_SP_WEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static void mmp_sspa_rx_disable(struct sspa_priv *sspa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned int sspa_sp = sspa->sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	sspa_sp &= ~SSPA_SP_S_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	sspa_sp |= SSPA_SP_WEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	__raw_writel(sspa_sp, sspa->rx_base + SSPA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int mmp_sspa_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	clk_prepare_enable(sspa->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	clk_prepare_enable(sspa->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static void mmp_sspa_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	clk_disable_unprepare(sspa->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	clk_disable_unprepare(sspa->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * Set the SSP ports SYSCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int mmp_sspa_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				    int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct device *dev = cpu_dai->component->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case MMP_SSPA_CLK_AUDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		ret = clk_set_rate(sspa->audio_clk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case MMP_SSPA_CLK_PLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case MMP_SSPA_CLK_VCXO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		/* not support yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int mmp_sspa_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				 int source, unsigned int freq_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				 unsigned int freq_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct device *dev = cpu_dai->component->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	switch (pll_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	case MMP_SYSCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		ret = clk_set_rate(sspa->sysclk, freq_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	case MMP_SSPA_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		ret = clk_set_rate(sspa->clk, freq_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * Set up the sspa dai format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int mmp_sspa_set_dai_fmt(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				 unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* reset port settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	sspa->sp   = SSPA_SP_WEN | SSPA_SP_S_RST | SSPA_SP_FFLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	sspa->ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		sspa->sp |= SSPA_SP_MSL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		sspa->sp |= SSPA_SP_FSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		sspa->ctrl |= SSPA_CTL_XDATDLY(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* Since we are configuring the timings for the format by hand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 * we have to defer some things until hw_params() where we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 * know parameters like the sample size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * Set the SSPA audio DMA parameters and sample size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * Can be called multiple times by oss emulation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int mmp_sspa_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			       struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			       struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct device *dev = dai->component->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	u32 sspa_ctrl = sspa->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int bitval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		bitval = SSPA_CTL_8_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		bits = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		bitval = SSPA_CTL_16_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case SNDRV_PCM_FORMAT_S24_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		bits = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		bitval = SSPA_CTL_24_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		bits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		bitval = SSPA_CTL_32_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (dev->of_node || params_channels(params) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		sspa_ctrl |= SSPA_CTL_XPH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	sspa_ctrl &= ~SSPA_CTL_XWDLEN1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	sspa_ctrl |= SSPA_CTL_XWDLEN1(bitval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	sspa_ctrl &= ~SSPA_CTL_XSSZ1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	sspa_ctrl |= SSPA_CTL_XSSZ1(bitval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	sspa_ctrl &= ~SSPA_CTL_XSSZ2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	sspa_ctrl |= SSPA_CTL_XSSZ2(bitval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	sspa->sp &= ~SSPA_SP_FWID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	sspa->sp |= SSPA_SP_FWID(bits - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	sspa->sp &= ~SSPA_TXSP_FPER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	sspa->sp |= SSPA_TXSP_FPER(bits * 2 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		clk_set_rate(sspa->clk, params_rate(params) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 					params_channels(params) * bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		__raw_writel(sspa_ctrl, sspa->tx_base + SSPA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		__raw_writel(0x1, sspa->tx_base + SSPA_FIFO_UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		__raw_writel(sspa_ctrl, sspa->rx_base + SSPA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		__raw_writel(0x0, sspa->rx_base + SSPA_FIFO_UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int mmp_sspa_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			     struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct sspa_priv *sspa = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		 * whatever playback or capture, must enable rx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		 * this is a hw issue, so need check if rx has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		 * enabled or not; if has been enabled by another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		 * stream, do not enable again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		if (!sspa->running_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			mmp_sspa_rx_enable(sspa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			mmp_sspa_tx_enable(sspa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		sspa->running_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		sspa->running_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			mmp_sspa_tx_disable(sspa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		/* have no capture stream, disable rx port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		if (!sspa->running_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			mmp_sspa_rx_disable(sspa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int mmp_sspa_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct sspa_priv *sspa = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	snd_soc_dai_init_dma_data(dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				&sspa->playback_dma_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 				&sspa->capture_dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	snd_soc_dai_set_drvdata(dai, sspa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MMP_SSPA_RATES SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MMP_SSPA_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		SNDRV_PCM_FMTBIT_S16_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		SNDRV_PCM_FMTBIT_S24_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct snd_soc_dai_ops mmp_sspa_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.startup	= mmp_sspa_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.shutdown	= mmp_sspa_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.trigger	= mmp_sspa_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.hw_params	= mmp_sspa_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.set_sysclk	= mmp_sspa_set_dai_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.set_pll	= mmp_sspa_set_dai_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.set_fmt	= mmp_sspa_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct snd_soc_dai_driver mmp_sspa_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.probe = mmp_sspa_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.channels_max = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.rates = MMP_SSPA_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.formats = MMP_SSPA_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		.rates = MMP_SSPA_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.formats = MMP_SSPA_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.ops = &mmp_sspa_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MMP_PCM_INFO (SNDRV_PCM_INFO_MMAP |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		SNDRV_PCM_INFO_MMAP_VALID |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		SNDRV_PCM_INFO_INTERLEAVED |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		SNDRV_PCM_INFO_PAUSE |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		SNDRV_PCM_INFO_RESUME |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		SNDRV_PCM_INFO_NO_PERIOD_WAKEUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct snd_pcm_hardware mmp_pcm_hardware[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.info			= MMP_PCM_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		.period_bytes_min	= 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		.period_bytes_max	= 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.periods_min		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.periods_max		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		.buffer_bytes_max	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.fifo_size		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		.info			= MMP_PCM_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		.period_bytes_min	= 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		.period_bytes_max	= 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.periods_min		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		.periods_max		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		.buffer_bytes_max	= 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		.fifo_size		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct snd_dmaengine_pcm_config mmp_pcm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.pcm_hardware = mmp_pcm_hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.prealloc_buffer_size = 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int mmp_pcm_mmap(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	return remap_pfn_range(vma, vma->vm_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		substream->dma_buffer.addr >> PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		vma->vm_end - vma->vm_start, vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int mmp_sspa_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			 struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	struct sspa_priv *sspa = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	pm_runtime_get_sync(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	/* we can only change the settings if the port is not in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	if ((__raw_readl(sspa->tx_base + SSPA_SP) & SSPA_SP_S_EN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	    (__raw_readl(sspa->rx_base + SSPA_SP) & SSPA_SP_S_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		dev_err(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			"can't change hardware dai format: stream is in use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	sspa->sp &= ~(SSPA_SP_S_RST | SSPA_SP_FFLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	__raw_writel(sspa->sp, sspa->tx_base + SSPA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	__raw_writel(sspa->sp, sspa->rx_base + SSPA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	 * FIXME: hw issue, for the tx serial port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	 * can not config the master/slave mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	 * so must clean this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	 * The master/slave mode has been set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	 * rx port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	__raw_writel(sspa->sp & ~SSPA_SP_MSL, sspa->tx_base + SSPA_SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	__raw_writel(sspa->ctrl, sspa->tx_base + SSPA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	__raw_writel(sspa->ctrl, sspa->rx_base + SSPA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int mmp_sspa_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 			  struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	pm_runtime_put_sync(component->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct snd_soc_component_driver mmp_sspa_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	.name		= "mmp-sspa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.mmap		= mmp_pcm_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	.open		= mmp_sspa_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	.close		= mmp_sspa_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int asoc_mmp_sspa_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	struct sspa_priv *sspa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	sspa = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 				sizeof(struct sspa_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	if (!sspa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		sspa->rx_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		if (IS_ERR(sspa->rx_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 			return PTR_ERR(sspa->rx_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		sspa->tx_base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		if (IS_ERR(sspa->tx_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 			return PTR_ERR(sspa->tx_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		sspa->clk = devm_clk_get(&pdev->dev, "bitclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		if (IS_ERR(sspa->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 			return PTR_ERR(sspa->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		sspa->audio_clk = devm_clk_get(&pdev->dev, "audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		if (IS_ERR(sspa->audio_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 			return PTR_ERR(sspa->audio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		if (res == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		sspa->rx_base = devm_ioremap(&pdev->dev, res->start, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 		if (!sspa->rx_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		sspa->tx_base = devm_ioremap(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 					     res->start + 0x80, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		if (!sspa->tx_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		sspa->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		if (IS_ERR(sspa->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 			return PTR_ERR(sspa->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		sspa->audio_clk = clk_get(NULL, "mmp-audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		if (IS_ERR(sspa->audio_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 			return PTR_ERR(sspa->audio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		sspa->sysclk = clk_get(NULL, "mmp-sysclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		if (IS_ERR(sspa->sysclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 			clk_put(sspa->audio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 			return PTR_ERR(sspa->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	platform_set_drvdata(pdev, sspa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	sspa->playback_dma_data.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	sspa->capture_dma_data.maxburst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	/* You know, these addresses are actually ignored. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	sspa->capture_dma_data.addr = SSPA_D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	sspa->playback_dma_data.addr = 0x80 + SSPA_D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 						      &mmp_pcm_config, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	ret = devm_snd_soc_register_component(&pdev->dev, &mmp_sspa_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 					      &mmp_sspa_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	clk_prepare_enable(sspa->audio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int asoc_mmp_sspa_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	struct sspa_priv *sspa = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	clk_disable_unprepare(sspa->audio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	clk_put(sspa->audio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	clk_put(sspa->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const struct of_device_id mmp_sspa_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	{ .compatible = "marvell,mmp-sspa" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MODULE_DEVICE_TABLE(of, mmp_sspa_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static struct platform_driver asoc_mmp_sspa_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		.name = "mmp-sspa-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		.of_match_table = of_match_ptr(mmp_sspa_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	.probe = asoc_mmp_sspa_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	.remove = asoc_mmp_sspa_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) module_platform_driver(asoc_mmp_sspa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) MODULE_DESCRIPTION("MMP SSPA SoC Interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MODULE_ALIAS("platform:mmp-sspa-dai");