^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _MXS_SAIF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _MXS_SAIF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SAIF_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SAIF_STAT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SAIF_DATA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SAIF_VERSION 0X30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* SAIF_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BM_SAIF_CTRL_SFTRST 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BM_SAIF_CTRL_CLKGATE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BP_SAIF_CTRL_BITCLK_MULT_RATE 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BP_SAIF_CTRL_RSRVD2 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BM_SAIF_CTRL_RSRVD2 0x00E00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BP_SAIF_CTRL_DMAWAIT_COUNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BM_SAIF_CTRL_LRCLK_PULSE 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BM_SAIF_CTRL_BIT_ORDER 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BM_SAIF_CTRL_DELAY 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BM_SAIF_CTRL_JUSTIFY 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BP_SAIF_CTRL_WORD_LENGTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BF_SAIF_CTRL_WORD_LENGTH(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BM_SAIF_CTRL_SLAVE_MODE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BM_SAIF_CTRL_READ_MODE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BM_SAIF_CTRL_RUN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* SAIF_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BM_SAIF_STAT_PRESENT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BP_SAIF_STAT_RSRVD2 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BM_SAIF_STAT_RSRVD2 0x7FFE0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BF_SAIF_STAT_RSRVD2(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (((v) << 17) & BM_SAIF_STAT_RSRVD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BM_SAIF_STAT_DMA_PREQ 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BP_SAIF_STAT_RSRVD1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BM_SAIF_STAT_RSRVD1 0x0000FF80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BF_SAIF_STAT_RSRVD1(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (((v) << 7) & BM_SAIF_STAT_RSRVD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BP_SAIF_STAT_RSRVD0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BM_SAIF_STAT_RSRVD0 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BF_SAIF_STAT_RSRVD0(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (((v) << 1) & BM_SAIF_STAT_RSRVD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BM_SAIF_STAT_BUSY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* SAFI_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BP_SAIF_DATA_PCM_RIGHT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BF_SAIF_DATA_PCM_RIGHT(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BP_SAIF_DATA_PCM_LEFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BF_SAIF_DATA_PCM_LEFT(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (((v) << 0) & BM_SAIF_DATA_PCM_LEFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* SAIF_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BP_SAIF_VERSION_MAJOR 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BM_SAIF_VERSION_MAJOR 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BF_SAIF_VERSION_MAJOR(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) (((v) << 24) & BM_SAIF_VERSION_MAJOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BP_SAIF_VERSION_MINOR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BM_SAIF_VERSION_MINOR 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BF_SAIF_VERSION_MINOR(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (((v) << 16) & BM_SAIF_VERSION_MINOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BP_SAIF_VERSION_STEP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BM_SAIF_VERSION_STEP 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BF_SAIF_VERSION_STEP(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (((v) << 0) & BM_SAIF_VERSION_STEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MXS_SAIF_MCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #include "mxs-pcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mxs_saif {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int mclk_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int master_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int ongoing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 fifo_underrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 fifo_overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MXS_SAIF_STATE_STOPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MXS_SAIF_STATE_RUNNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) extern int mxs_saif_put_mclk(unsigned int saif_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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