^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "mxs-saif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MXS_SET_ADDR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MXS_CLR_ADDR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct mxs_saif *mxs_saif[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * SAIF is a little different with other normal SOC DAIs on clock using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * For MXS, two SAIF modules are instantiated on-chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Each SAIF has a set of clock pins and can be operating in master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * mode simultaneously if they are connected to different off-chip codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Also, one of the two SAIFs can master or drive the clock pins while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * other SAIF, in slave mode, receives clocking from the master SAIF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * This also means that both SAIFs must operate at the same sample rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * We abstract this as each saif has a master, the master could be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * itself or other saifs. In the generic saif driver, saif does not need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * to know the different clkmux. Saif only needs to know who is its master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * and operating its master to generate the proper clock rate for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * The master id is provided in mach-specific layer according to different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * clkmux setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) switch (clk_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case MXS_SAIF_MCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) saif->mclk = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * is provided by other SAIF, we provide a interface here to get its master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * from its master_id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Note that the master could be itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return mxs_saif[saif->master_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Set SAIF clock and MCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int mxs_saif_set_clk(struct mxs_saif *saif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct mxs_saif *master_saif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Set master saif to generate proper clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) master_saif = mxs_saif_get_master(saif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!master_saif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Checking if can playback and capture simutaneously */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (master_saif->ongoing && rate != master_saif->cur_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(saif->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "can not change clock, master saif%d(rate %d) is ongoing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) master_saif->id, master_saif->cur_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) scr = __raw_readl(master_saif->base + SAIF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Set SAIF clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * The SAIF clock should be either 384*fs or 512*fs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * If MCLK is used, the SAIF clk ratio needs to match mclk ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * If MCLK is not used, we just set saif clk to 512*fs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = clk_prepare_enable(master_saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (master_saif->mclk_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) switch (mclk / rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = clk_set_rate(master_saif->clk, 512 * rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case 48:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case 96:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case 192:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case 384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = clk_set_rate(master_saif->clk, 384 * rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* SAIF MCLK should be a sub-rate of 512x or 384x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clk_disable_unprepare(master_saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = clk_set_rate(master_saif->clk, 512 * rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk_disable_unprepare(master_saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) master_saif->cur_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!master_saif->mclk_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __raw_writel(scr, master_saif->base + SAIF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Program the over-sample rate for MCLK output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * The available MCLK range is 32x, 48x... 512x. The rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * could be from 8kHz to 192kH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (mclk / rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case 512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case 48:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case 96:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case 192:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case 384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __raw_writel(scr, master_saif->base + SAIF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Put and disable MCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int mxs_saif_put_mclk(unsigned int saif_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct mxs_saif *saif = mxs_saif[saif_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!saif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) stat = __raw_readl(saif->base + SAIF_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (stat & BM_SAIF_STAT_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_err(saif->dev, "error: busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clk_disable_unprepare(saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* disable MCLK output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __raw_writel(BM_SAIF_CTRL_CLKGATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) saif->base + SAIF_CTRL + MXS_SET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __raw_writel(BM_SAIF_CTRL_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) saif->base + SAIF_CTRL + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) saif->mclk_in_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Get MCLK and set clock rate, then enable it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * This interface is used for codecs who are using MCLK provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * by saif.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct mxs_saif *saif = mxs_saif[saif_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct mxs_saif *master_saif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!saif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Clear Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __raw_writel(BM_SAIF_CTRL_SFTRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) saif->base + SAIF_CTRL + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* FIXME: need clear clk gate for register r/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __raw_writel(BM_SAIF_CTRL_CLKGATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) saif->base + SAIF_CTRL + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) master_saif = mxs_saif_get_master(saif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (saif != master_saif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(saif->dev, "can not get mclk from a non-master saif\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) stat = __raw_readl(saif->base + SAIF_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (stat & BM_SAIF_STAT_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_err(saif->dev, "error: busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) saif->mclk_in_use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = mxs_saif_set_clk(saif, mclk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = clk_prepare_enable(saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* enable MCLK output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __raw_writel(BM_SAIF_CTRL_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) saif->base + SAIF_CTRL + MXS_SET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * SAIF DAI format configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Should only be called when port is inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 scr, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 scr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) stat = __raw_readl(saif->base + SAIF_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (stat & BM_SAIF_STAT_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_err(cpu_dai->dev, "error: busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* If SAIF1 is configured as slave, the clk gate needs to be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * before the register can be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (saif->id != saif->master_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __raw_writel(BM_SAIF_CTRL_SFTRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) saif->base + SAIF_CTRL + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __raw_writel(BM_SAIF_CTRL_CLKGATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) saif->base + SAIF_CTRL + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) scr0 = __raw_readl(saif->base + SAIF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) scr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* DAI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* data frame low 1clk before data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) scr |= BM_SAIF_CTRL_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* data frame high with data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) scr &= ~BM_SAIF_CTRL_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) scr &= ~BM_SAIF_CTRL_JUSTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* DAI clock inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) scr |= BM_SAIF_CTRL_BITCLK_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) scr |= BM_SAIF_CTRL_BITCLK_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Note: We simply just support master mode since SAIF TX can only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * work as master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Here the master is relative to codec side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Saif internally could be slave when working on EXTMASTER mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * We just hide this to machine driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (saif->id == saif->master_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) scr |= BM_SAIF_CTRL_SLAVE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int mxs_saif_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* clear error status to 0 for each re-open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) saif->fifo_underrun = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) saif->fifo_overrun = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Clear Reset for normal operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __raw_writel(BM_SAIF_CTRL_SFTRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) saif->base + SAIF_CTRL + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* clear clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __raw_writel(BM_SAIF_CTRL_CLKGATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) saif->base + SAIF_CTRL + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = clk_prepare(saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void mxs_saif_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) clk_unprepare(saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Should only be called when port is inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * although can be called multiple times by upper layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct mxs_saif *master_saif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 scr, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) master_saif = mxs_saif_get_master(saif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!master_saif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* mclk should already be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!saif->mclk && saif->mclk_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(cpu_dai->dev, "set mclk first\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) stat = __raw_readl(saif->base + SAIF_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(cpu_dai->dev, "error: busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Set saif clk based on sample rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * If mclk is used, we also set mclk, if not, saif->mclk is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * default 0, means not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(cpu_dai->dev, "unable to get proper clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (saif != master_saif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * Set an initial clock rate for the saif internal logic to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * properly. This is important when working in EXTMASTER mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * that uses the other saif's BITCLK&LRCLK but it still needs a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * basic clock which should be fast enough for the internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = clk_enable(saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = clk_set_rate(saif->clk, 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) clk_disable(saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = clk_prepare(master_saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) scr = __raw_readl(saif->base + SAIF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case SNDRV_PCM_FORMAT_S20_3LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case SNDRV_PCM_FORMAT_S24_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Tx/Rx config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* enable TX mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) scr &= ~BM_SAIF_CTRL_READ_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* enable RX mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) scr |= BM_SAIF_CTRL_READ_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __raw_writel(scr, saif->base + SAIF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int mxs_saif_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* enable FIFO error irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) saif->base + SAIF_CTRL + MXS_SET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct snd_soc_dai *cpu_dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct mxs_saif *master_saif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) master_saif = mxs_saif_get_master(saif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (!master_saif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (saif->state == MXS_SAIF_STATE_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_dbg(cpu_dai->dev, "start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ret = clk_enable(master_saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_err(saif->dev, "Failed to enable master clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * If the saif's master is not itself, we also need to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * itself clk for its internal basic logic to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (saif != master_saif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = clk_enable(saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(saif->dev, "Failed to enable master clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) clk_disable(master_saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) __raw_writel(BM_SAIF_CTRL_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) saif->base + SAIF_CTRL + MXS_SET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!master_saif->mclk_in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) __raw_writel(BM_SAIF_CTRL_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * write data to saif data register to trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * For 24-bit format the 32-bit FIFO register stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * only one channel, so we need to write twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * This is also safe for the other non 24-bit formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) __raw_writel(0, saif->base + SAIF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __raw_writel(0, saif->base + SAIF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * read data from saif data register to trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * the receive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * For 24-bit format the 32-bit FIFO register stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * only one channel, so we need to read twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * This is also safe for the other non 24-bit formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) __raw_readl(saif->base + SAIF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __raw_readl(saif->base + SAIF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) master_saif->ongoing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) saif->state = MXS_SAIF_STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __raw_readl(saif->base + SAIF_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) __raw_readl(saif->base + SAIF_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) __raw_readl(master_saif->base + SAIF_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) __raw_readl(master_saif->base + SAIF_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (saif->state == MXS_SAIF_STATE_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_dbg(cpu_dai->dev, "stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* wait a while for the current sample to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) delay = USEC_PER_SEC / master_saif->cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!master_saif->mclk_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) __raw_writel(BM_SAIF_CTRL_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) udelay(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) clk_disable(master_saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (saif != master_saif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) __raw_writel(BM_SAIF_CTRL_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) saif->base + SAIF_CTRL + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) udelay(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) clk_disable(saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) master_saif->ongoing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) saif->state = MXS_SAIF_STATE_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define MXS_SAIF_FORMATS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SNDRV_PCM_FMTBIT_S24_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .startup = mxs_saif_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .shutdown = mxs_saif_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .trigger = mxs_saif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .prepare = mxs_saif_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .hw_params = mxs_saif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .set_sysclk = mxs_saif_set_dai_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .set_fmt = mxs_saif_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct mxs_saif *saif = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) snd_soc_dai_set_drvdata(dai, saif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static struct snd_soc_dai_driver mxs_saif_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .name = "mxs-saif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .probe = mxs_saif_dai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .rates = MXS_SAIF_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .formats = MXS_SAIF_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .rates = MXS_SAIF_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .formats = MXS_SAIF_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .ops = &mxs_saif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const struct snd_soc_component_driver mxs_saif_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .name = "mxs-saif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct mxs_saif *saif = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) stat = __raw_readl(saif->base + SAIF_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) saif->base + SAIF_STAT + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) saif->base + SAIF_STAT + MXS_CLR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) __raw_readl(saif->base + SAIF_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) __raw_readl(saif->base + SAIF_STAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int mxs_saif_mclk_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct mxs_saif *saif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) __clk_get_name(saif->clk), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) saif->base + SAIF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) BP_SAIF_CTRL_BITCLK_MULT_RATE, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (ret == -EEXIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_err(&pdev->dev, "failed to register mclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int mxs_saif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct mxs_saif *saif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct device_node *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!saif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ret = of_alias_get_id(np, "saif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) saif->id = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (saif->id >= ARRAY_SIZE(mxs_saif)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_err(&pdev->dev, "get wrong saif id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * If there is no "fsl,saif-master" phandle, it's a saif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * master. Otherwise, it's a slave and its phandle points
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * to the master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) master = of_parse_phandle(np, "fsl,saif-master", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) saif->master_id = saif->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = of_alias_get_id(master, "saif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) saif->master_id = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dev_err(&pdev->dev, "get wrong master id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mxs_saif[saif->id] = saif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) saif->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (IS_ERR(saif->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = PTR_ERR(saif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err(&pdev->dev, "Cannot get the clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) saif->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (IS_ERR(saif->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return PTR_ERR(saif->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) saif->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_name(&pdev->dev), saif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(&pdev->dev, "failed to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) platform_set_drvdata(pdev, saif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* We only support saif0 being tx and clock master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (saif->id == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = mxs_saif_mclk_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_warn(&pdev->dev, "failed to init clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) &mxs_saif_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_err(&pdev->dev, "register DAI failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = mxs_pcm_platform_register(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const struct of_device_id mxs_saif_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) { .compatible = "fsl,imx28-saif", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct platform_driver mxs_saif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .probe = mxs_saif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .name = "mxs-saif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .of_match_table = mxs_saif_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) module_platform_driver(mxs_saif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) MODULE_AUTHOR("Freescale Semiconductor, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) MODULE_DESCRIPTION("MXS ASoC SAIF driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) MODULE_ALIAS("platform:mxs-saif");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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