^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2019 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "meson-codec-glue.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define G12A_TOHDMITX_DRV_NAME "g12a-tohdmitx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TOHDMITX_CTRL0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CTRL0_ENABLE_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CTRL0_I2S_DAT_SEL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CTRL0_I2S_DAT_SEL (0x3 << CTRL0_I2S_DAT_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CTRL0_I2S_LRCLK_SEL GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CTRL0_I2S_BLK_CAP_INV BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CTRL0_I2S_BCLK_O_INV BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CTRL0_I2S_BCLK_SEL GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CTRL0_SPDIF_CLK_CAP_INV BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CTRL0_SPDIF_CLK_O_INV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CTRL0_SPDIF_SEL_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CTRL0_SPDIF_SEL (0x1 << CTRL0_SPDIF_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CTRL0_SPDIF_CLK_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const char * const g12a_tohdmitx_i2s_mux_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "I2S A", "I2S B", "I2S C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int g12a_tohdmitx_i2s_mux_put_enum(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct snd_soc_component *component =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) snd_soc_dapm_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct snd_soc_dapm_context *dapm =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) snd_soc_dapm_kcontrol_dapm(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int mux, changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) changed = snd_soc_component_test_bits(component, e->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) CTRL0_I2S_DAT_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FIELD_PREP(CTRL0_I2S_DAT_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Force disconnect of the mux while updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) snd_soc_component_update_bits(component, e->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) CTRL0_I2S_DAT_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) CTRL0_I2S_LRCLK_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CTRL0_I2S_BCLK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FIELD_PREP(CTRL0_I2S_DAT_SEL, mux) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FIELD_PREP(CTRL0_I2S_LRCLK_SEL, mux) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FIELD_PREP(CTRL0_I2S_BCLK_SEL, mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static SOC_ENUM_SINGLE_DECL(g12a_tohdmitx_i2s_mux_enum, TOHDMITX_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CTRL0_I2S_DAT_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) g12a_tohdmitx_i2s_mux_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct snd_kcontrol_new g12a_tohdmitx_i2s_mux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SOC_DAPM_ENUM_EXT("I2S Source", g12a_tohdmitx_i2s_mux_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) snd_soc_dapm_get_enum_double,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) g12a_tohdmitx_i2s_mux_put_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char * const g12a_tohdmitx_spdif_mux_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "SPDIF A", "SPDIF B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int g12a_tohdmitx_spdif_mux_put_enum(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct snd_soc_component *component =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) snd_soc_dapm_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct snd_soc_dapm_context *dapm =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) snd_soc_dapm_kcontrol_dapm(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int mux, changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) changed = snd_soc_component_test_bits(component, TOHDMITX_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CTRL0_SPDIF_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FIELD_PREP(CTRL0_SPDIF_SEL, mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Force disconnect of the mux while updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) snd_soc_component_update_bits(component, TOHDMITX_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CTRL0_SPDIF_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CTRL0_SPDIF_CLK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FIELD_PREP(CTRL0_SPDIF_SEL, mux) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FIELD_PREP(CTRL0_SPDIF_CLK_SEL, mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static SOC_ENUM_SINGLE_DECL(g12a_tohdmitx_spdif_mux_enum, TOHDMITX_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CTRL0_SPDIF_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) g12a_tohdmitx_spdif_mux_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct snd_kcontrol_new g12a_tohdmitx_spdif_mux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SOC_DAPM_ENUM_EXT("SPDIF Source", g12a_tohdmitx_spdif_mux_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) snd_soc_dapm_get_enum_double,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) g12a_tohdmitx_spdif_mux_put_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct snd_kcontrol_new g12a_tohdmitx_out_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SOC_DAPM_SINGLE_AUTODISABLE("Switch", TOHDMITX_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CTRL0_ENABLE_SHIFT, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct snd_soc_dapm_widget g12a_tohdmitx_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SND_SOC_DAPM_MUX("I2S SRC", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) &g12a_tohdmitx_i2s_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SND_SOC_DAPM_SWITCH("I2S OUT EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) &g12a_tohdmitx_out_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SND_SOC_DAPM_MUX("SPDIF SRC", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &g12a_tohdmitx_spdif_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SND_SOC_DAPM_SWITCH("SPDIF OUT EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &g12a_tohdmitx_out_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct snd_soc_dai_ops g12a_tohdmitx_input_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .hw_params = meson_codec_glue_input_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .set_fmt = meson_codec_glue_input_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct snd_soc_dai_ops g12a_tohdmitx_output_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .startup = meson_codec_glue_output_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TOHDMITX_SPDIF_FORMATS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TOHDMITX_I2S_FORMATS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TOHDMITX_STREAM(xname, xsuffix, xfmt, xchmax) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .stream_name = xname " " xsuffix, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .channels_min = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .channels_max = (xchmax), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .rate_min = 8000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .rate_max = 192000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .formats = (xfmt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TOHDMITX_IN(xname, xid, xfmt, xchmax) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .id = (xid), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .playback = TOHDMITX_STREAM(xname, "Playback", xfmt, xchmax), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .ops = &g12a_tohdmitx_input_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .probe = meson_codec_glue_input_dai_probe, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .remove = meson_codec_glue_input_dai_remove, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TOHDMITX_OUT(xname, xid, xfmt, xchmax) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .id = (xid), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .capture = TOHDMITX_STREAM(xname, "Capture", xfmt, xchmax), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .ops = &g12a_tohdmitx_output_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct snd_soc_dai_driver g12a_tohdmitx_dai_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) TOHDMITX_IN("I2S IN A", TOHDMITX_I2S_IN_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) TOHDMITX_I2S_FORMATS, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) TOHDMITX_IN("I2S IN B", TOHDMITX_I2S_IN_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) TOHDMITX_I2S_FORMATS, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) TOHDMITX_IN("I2S IN C", TOHDMITX_I2S_IN_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) TOHDMITX_I2S_FORMATS, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) TOHDMITX_OUT("I2S OUT", TOHDMITX_I2S_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) TOHDMITX_I2S_FORMATS, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) TOHDMITX_IN("SPDIF IN A", TOHDMITX_SPDIF_IN_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) TOHDMITX_SPDIF_FORMATS, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) TOHDMITX_IN("SPDIF IN B", TOHDMITX_SPDIF_IN_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) TOHDMITX_SPDIF_FORMATS, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) TOHDMITX_OUT("SPDIF OUT", TOHDMITX_SPDIF_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) TOHDMITX_SPDIF_FORMATS, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int g12a_tohdmi_component_probe(struct snd_soc_component *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Initialize the static clock parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return snd_soc_component_write(c, TOHDMITX_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CTRL0_I2S_BLK_CAP_INV | CTRL0_SPDIF_CLK_CAP_INV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct snd_soc_dapm_route g12a_tohdmitx_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { "I2S SRC", "I2S A", "I2S IN A Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { "I2S SRC", "I2S B", "I2S IN B Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { "I2S SRC", "I2S C", "I2S IN C Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { "I2S OUT EN", "Switch", "I2S SRC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { "I2S OUT Capture", NULL, "I2S OUT EN" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { "SPDIF SRC", "SPDIF A", "SPDIF IN A Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { "SPDIF SRC", "SPDIF B", "SPDIF IN B Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { "SPDIF OUT EN", "Switch", "SPDIF SRC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { "SPDIF OUT Capture", NULL, "SPDIF OUT EN" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct snd_soc_component_driver g12a_tohdmitx_component_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .probe = g12a_tohdmi_component_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .dapm_widgets = g12a_tohdmitx_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .num_dapm_widgets = ARRAY_SIZE(g12a_tohdmitx_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .dapm_routes = g12a_tohdmitx_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .num_dapm_routes = ARRAY_SIZE(g12a_tohdmitx_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .endianness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .non_legacy_dai_naming = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct regmap_config g12a_tohdmitx_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct of_device_id g12a_tohdmitx_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { .compatible = "amlogic,g12a-tohdmitx", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_DEVICE_TABLE(of, g12a_tohdmitx_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int g12a_tohdmitx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = device_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) map = devm_regmap_init_mmio(dev, regs, &g12a_tohdmitx_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_err(dev, "failed to init regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PTR_ERR(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return devm_snd_soc_register_component(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) &g12a_tohdmitx_component_drv, g12a_tohdmitx_dai_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ARRAY_SIZE(g12a_tohdmitx_dai_drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct platform_driver g12a_tohdmitx_pdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .name = G12A_TOHDMITX_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .of_match_table = g12a_tohdmitx_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .probe = g12a_tohdmitx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) module_platform_driver(g12a_tohdmitx_pdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_DESCRIPTION("Amlogic G12a To HDMI Tx Control Codec Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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