Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2020 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <dt-bindings/sound/meson-g12a-toacodec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "axg-tdm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "meson-codec-glue.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define G12A_TOACODEC_DRV_NAME "g12a-toacodec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TOACODEC_CTRL0			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define  CTRL0_ENABLE_SHIFT		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define  CTRL0_DAT_SEL_SHIFT		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define  CTRL0_DAT_SEL			(0x3 << CTRL0_DAT_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define  CTRL0_LANE_SEL			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define  CTRL0_LRCLK_SEL		GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define  CTRL0_BLK_CAP_INV		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define  CTRL0_BCLK_O_INV		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define  CTRL0_BCLK_SEL			GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define  CTRL0_MCLK_SEL			GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TOACODEC_OUT_CHMAX		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static const char * const g12a_toacodec_mux_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	"I2S A", "I2S B", "I2S C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static int g12a_toacodec_mux_put_enum(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 				      struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct snd_soc_component *component =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		snd_soc_dapm_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct snd_soc_dapm_context *dapm =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		snd_soc_dapm_kcontrol_dapm(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int mux, changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	changed = snd_soc_component_test_bits(component, e->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 					      CTRL0_DAT_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 					      FIELD_PREP(CTRL0_DAT_SEL, mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (!changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/* Force disconnect of the mux while updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	snd_soc_component_update_bits(component, e->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				      CTRL0_DAT_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 				      CTRL0_LRCLK_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 				      CTRL0_BCLK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 				      FIELD_PREP(CTRL0_DAT_SEL, mux) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 				      FIELD_PREP(CTRL0_LRCLK_SEL, mux) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 				      FIELD_PREP(CTRL0_BCLK_SEL, mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * FIXME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * On this soc, the glue gets the MCLK directly from the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * controller instead of going the through the TDM interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * Here we assume interface A uses clock A, etc ... While it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * true for now, it could be different. Instead the glue should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * find out the clock used by the interface and select the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * source. For that, we will need regmap backed clock mux which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * is a work in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	snd_soc_component_update_bits(component, e->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				      CTRL0_MCLK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				      FIELD_PREP(CTRL0_MCLK_SEL, mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static SOC_ENUM_SINGLE_DECL(g12a_toacodec_mux_enum, TOACODEC_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			    CTRL0_DAT_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			    g12a_toacodec_mux_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static const struct snd_kcontrol_new g12a_toacodec_mux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	SOC_DAPM_ENUM_EXT("Source", g12a_toacodec_mux_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			  snd_soc_dapm_get_enum_double,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			  g12a_toacodec_mux_put_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static const struct snd_kcontrol_new g12a_toacodec_out_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", TOACODEC_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				    CTRL0_ENABLE_SHIFT, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct snd_soc_dapm_widget g12a_toacodec_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	SND_SOC_DAPM_MUX("SRC", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			 &g12a_toacodec_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	SND_SOC_DAPM_SWITCH("OUT EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			    &g12a_toacodec_out_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int g12a_toacodec_input_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 					 struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 					 struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct meson_codec_glue_input *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ret = meson_codec_glue_input_hw_params(substream, params, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* The glue will provide 1 lane out of the 4 to the output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	data = meson_codec_glue_input_get_data(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	data->params.channels_min = min_t(unsigned int, TOACODEC_OUT_CHMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 					data->params.channels_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	data->params.channels_max = min_t(unsigned int, TOACODEC_OUT_CHMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 					data->params.channels_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct snd_soc_dai_ops g12a_toacodec_input_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.hw_params	= g12a_toacodec_input_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.set_fmt	= meson_codec_glue_input_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct snd_soc_dai_ops g12a_toacodec_output_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.startup	= meson_codec_glue_output_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TOACODEC_STREAM(xname, xsuffix, xchmax)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.stream_name	= xname " " xsuffix,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.channels_min	= 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.channels_max	= (xchmax),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.rate_min       = 5512,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.rate_max	= 192000,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.formats	= AXG_TDM_FORMATS,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TOACODEC_INPUT(xname, xid) {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.name = xname,							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.id = (xid),							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.playback = TOACODEC_STREAM(xname, "Playback", 8),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.ops = &g12a_toacodec_input_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.probe = meson_codec_glue_input_dai_probe,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.remove = meson_codec_glue_input_dai_remove,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TOACODEC_OUTPUT(xname, xid) {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.name = xname,							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.id = (xid),							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.capture = TOACODEC_STREAM(xname, "Capture", TOACODEC_OUT_CHMAX), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.ops = &g12a_toacodec_output_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct snd_soc_dai_driver g12a_toacodec_dai_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	TOACODEC_INPUT("IN A", TOACODEC_IN_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	TOACODEC_INPUT("IN B", TOACODEC_IN_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	TOACODEC_INPUT("IN C", TOACODEC_IN_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	TOACODEC_OUTPUT("OUT", TOACODEC_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int g12a_toacodec_component_probe(struct snd_soc_component *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* Initialize the static clock parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return snd_soc_component_write(c, TOACODEC_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				       CTRL0_BLK_CAP_INV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct snd_soc_dapm_route g12a_toacodec_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	{ "SRC", "I2S A", "IN A Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{ "SRC", "I2S B", "IN B Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	{ "SRC", "I2S C", "IN C Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	{ "OUT EN", "Switch", "SRC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{ "OUT Capture", NULL, "OUT EN" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct snd_kcontrol_new g12a_toacodec_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct snd_soc_component_driver g12a_toacodec_component_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.probe			= g12a_toacodec_component_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.controls		= g12a_toacodec_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.num_controls		= ARRAY_SIZE(g12a_toacodec_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.dapm_widgets		= g12a_toacodec_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.num_dapm_widgets	= ARRAY_SIZE(g12a_toacodec_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.dapm_routes		= g12a_toacodec_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.num_dapm_routes	= ARRAY_SIZE(g12a_toacodec_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.endianness		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.non_legacy_dai_naming	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct regmap_config g12a_toacodec_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.reg_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.reg_stride	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct of_device_id g12a_toacodec_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	{ .compatible = "amlogic,g12a-toacodec", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_DEVICE_TABLE(of, g12a_toacodec_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int g12a_toacodec_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret = device_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	map = devm_regmap_init_mmio(dev, regs, &g12a_toacodec_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		dev_err(dev, "failed to init regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			PTR_ERR(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return devm_snd_soc_register_component(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			&g12a_toacodec_component_drv, g12a_toacodec_dai_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			ARRAY_SIZE(g12a_toacodec_dai_drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct platform_driver g12a_toacodec_pdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.name = G12A_TOACODEC_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.of_match_table = g12a_toacodec_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.probe = g12a_toacodec_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) module_platform_driver(g12a_toacodec_pdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_DESCRIPTION("Amlogic G12a To Internal DAC Codec Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MODULE_LICENSE("GPL v2");