Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018 Baylibre SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _MESON_AXG_TDM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _MESON_AXG_TDM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AXG_TDM_NUM_LANES	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AXG_TDM_CHANNEL_MAX	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AXG_TDM_RATES		(SNDRV_PCM_RATE_5512 |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 				 SNDRV_PCM_RATE_8000_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AXG_TDM_FORMATS		(SNDRV_PCM_FMTBIT_S8 |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 				 SNDRV_PCM_FMTBIT_S16_LE |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 				 SNDRV_PCM_FMTBIT_S20_LE |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 				 SNDRV_PCM_FMTBIT_S24_LE |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 				 SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct axg_tdm_iface {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	struct clk *lrclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	unsigned long mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	/* format is common to all the DAIs of the iface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	unsigned int fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	unsigned int slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	unsigned int slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	/* For component wide symmetry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline bool axg_tdm_lrclk_invert(unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	return ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		!!(fmt & (SND_SOC_DAIFMT_IB_IF | SND_SOC_DAIFMT_NB_IF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline bool axg_tdm_sclk_invert(unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	return fmt & (SND_SOC_DAIFMT_IB_IF | SND_SOC_DAIFMT_IB_NF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct axg_tdm_stream {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	struct axg_tdm_iface *iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	struct list_head formatter_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	unsigned int channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	unsigned int physical_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	u32 *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	bool ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct axg_tdm_stream *axg_tdm_stream_alloc(struct axg_tdm_iface *iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void axg_tdm_stream_free(struct axg_tdm_stream *ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int axg_tdm_stream_start(struct axg_tdm_stream *ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void axg_tdm_stream_stop(struct axg_tdm_stream *ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline int axg_tdm_stream_reset(struct axg_tdm_stream *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	axg_tdm_stream_stop(ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	return axg_tdm_stream_start(ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 			  u32 *rx_mask, unsigned int slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 			  unsigned int slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif /* _MESON_AXG_TDM_H */