Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "axg-tdm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	TDM_IFACE_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	TDM_IFACE_LOOPBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static unsigned int axg_tdm_slots_total(u32 *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	unsigned int slots = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	if (!mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	/* Count the total number of slots provided by all 4 lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	for (i = 0; i < AXG_TDM_NUM_LANES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		slots += hweight32(mask[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	return slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 			  u32 *rx_mask, unsigned int slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			  unsigned int slot_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct axg_tdm_stream *tx = (struct axg_tdm_stream *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		dai->playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct axg_tdm_stream *rx = (struct axg_tdm_stream *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		dai->capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned int tx_slots, rx_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int fmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	tx_slots = axg_tdm_slots_total(tx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	rx_slots = axg_tdm_slots_total(rx_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* We should at least have a slot for a valid interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (!tx_slots && !rx_slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		dev_err(dai->dev, "interface has no slot\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	iface->slots = slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	switch (slot_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		slot_width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		fmt |= SNDRV_PCM_FMTBIT_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		fmt |= SNDRV_PCM_FMTBIT_S24_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		fmt |= SNDRV_PCM_FMTBIT_S20_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		fmt |= SNDRV_PCM_FMTBIT_S16_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		fmt |= SNDRV_PCM_FMTBIT_S8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	iface->slot_width = slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* Amend the dai driver and let dpcm merge do its job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		tx->mask = tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		dai->driver->playback.channels_max = tx_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		dai->driver->playback.formats = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		rx->mask = rx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		dai->driver->capture.channels_max = rx_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		dai->driver->capture.formats = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 				    unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		if (!iface->mclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			dev_warn(dai->dev, "master clock not provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			ret = clk_set_rate(iface->mclk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				iface->mclk_rate = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case SND_SOC_DAIFMT_CBS_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		if (!iface->mclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			dev_err(dai->dev, "cpu clock master: mclk missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case SND_SOC_DAIFMT_CBM_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	case SND_SOC_DAIFMT_CBS_CFM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case SND_SOC_DAIFMT_CBM_CFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	iface->fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				 struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct axg_tdm_stream *ts =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (!axg_tdm_slots_total(ts->mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		dev_err(dai->dev, "interface has not slots\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Apply component wide rate symmetry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (snd_soc_component_active(dai->component)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		ret = snd_pcm_hw_constraint_single(substream->runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 						   SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 						   iface->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			dev_err(dai->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				"can't set iface rate constraint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				    struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				    struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned int width = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* Save rate and sample_bits for component symmetry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	iface->rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* Make sure this interface can cope with the stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (axg_tdm_slots_total(ts->mask) < channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		dev_err(dai->dev, "not enough slots for channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (iface->slot_width < width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		dev_err(dai->dev, "incompatible slots width for stream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* Save the parameter for tdmout/tdmin widgets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ts->physical_width = params_physical_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ts->width = params_width(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ts->channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 				   struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	unsigned int ratio_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	ret = clk_set_rate(iface->lrclk, params_rate(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		/* 50% duty cycle ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		ratio_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		 * A zero duty cycle ratio will result in setting the mininum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		 * ratio possible which, for this clock, is 1 cycle of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		 * parent bclk clock high and the rest low, This is exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		 * what we want here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		ratio_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		dev_err(dai->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			"setting sample clock duty cycle failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/* Set sample clock inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ret = clk_set_phase(iface->lrclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			    axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		dev_err(dai->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			"setting sample clock phase failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				  struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	unsigned long srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	srate = iface->slots * iface->slot_width * params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (!iface->mclk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		/* If no specific mclk is requested, default to bit clock * 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		clk_set_rate(iface->mclk, 4 * srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		/* Check if we can actually get the bit clock from mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (iface->mclk_rate % srate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			dev_err(dai->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				"can't derive sclk %lu from mclk %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				srate, iface->mclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	ret = clk_set_rate(iface->sclk, srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* Set the bit clock inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ret = clk_set_phase(iface->sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			    axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 				   struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 				   struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	case SND_SOC_DAIFMT_RIGHT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (iface->slots > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			dev_err(dai->dev, "bad slot number for format: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 				iface->slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	case SND_SOC_DAIFMT_DSP_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		dev_err(dai->dev, "unsupported dai format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	ret = axg_tdm_iface_set_stream(substream, params, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if ((iface->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	    SND_SOC_DAIFMT_CBS_CFS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		ret = axg_tdm_iface_set_sclk(dai, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		ret = axg_tdm_iface_set_lrclk(dai, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				 struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	/* Stop all attached formatters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	axg_tdm_stream_stop(ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int axg_tdm_iface_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 				 struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	/* Force all attached formatters to update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	return axg_tdm_stream_reset(ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (dai->capture_dma_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		axg_tdm_stream_free(dai->capture_dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (dai->playback_dma_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		axg_tdm_stream_free(dai->playback_dma_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (dai->capture_widget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		dai->capture_dma_data = axg_tdm_stream_alloc(iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		if (!dai->capture_dma_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (dai->playback_widget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		dai->playback_dma_data = axg_tdm_stream_alloc(iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		if (!dai->playback_dma_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			axg_tdm_iface_remove_dai(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.set_sysclk	= axg_tdm_iface_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.set_fmt	= axg_tdm_iface_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.startup	= axg_tdm_iface_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.hw_params	= axg_tdm_iface_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.prepare	= axg_tdm_iface_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.hw_free	= axg_tdm_iface_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* TDM Backend DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	[TDM_IFACE_PAD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.name = "TDM Pad",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		.playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 			.stream_name	= "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 			.channels_min	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 			.channels_max	= AXG_TDM_CHANNEL_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			.rates		= AXG_TDM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			.formats	= AXG_TDM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			.stream_name	= "Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			.channels_min	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			.channels_max	= AXG_TDM_CHANNEL_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			.rates		= AXG_TDM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			.formats	= AXG_TDM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		.id = TDM_IFACE_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		.ops = &axg_tdm_iface_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		.probe = axg_tdm_iface_probe_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		.remove = axg_tdm_iface_remove_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	[TDM_IFACE_LOOPBACK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		.name = "TDM Loopback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		.capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 			.stream_name	= "Loopback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			.channels_min	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			.channels_max	= AXG_TDM_CHANNEL_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 			.rates		= AXG_TDM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 			.formats	= AXG_TDM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		.id = TDM_IFACE_LOOPBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		.ops = &axg_tdm_iface_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		.probe = axg_tdm_iface_probe_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		.remove = axg_tdm_iface_remove_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 					enum snd_soc_bias_level level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	enum snd_soc_bias_level now =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		snd_soc_component_get_bias_level(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	switch (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	case SND_SOC_BIAS_PREPARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		if (now == SND_SOC_BIAS_STANDBY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 			ret = clk_prepare_enable(iface->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	case SND_SOC_BIAS_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		if (now == SND_SOC_BIAS_PREPARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 			clk_disable_unprepare(iface->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	case SND_SOC_BIAS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	case SND_SOC_BIAS_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const struct snd_soc_dapm_widget axg_tdm_iface_dapm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	SND_SOC_DAPM_SIGGEN("Playback Signal"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct snd_soc_dapm_route axg_tdm_iface_dapm_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	{ "Loopback", NULL, "Playback Signal" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	.dapm_widgets		= axg_tdm_iface_dapm_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	.num_dapm_widgets	= ARRAY_SIZE(axg_tdm_iface_dapm_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	.dapm_routes		= axg_tdm_iface_dapm_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	.num_dapm_routes	= ARRAY_SIZE(axg_tdm_iface_dapm_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	.set_bias_level		= axg_tdm_iface_set_bias_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const struct of_device_id axg_tdm_iface_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	{ .compatible = "amlogic,axg-tdm-iface", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int axg_tdm_iface_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	struct snd_soc_dai_driver *dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	struct axg_tdm_iface *iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	if (!iface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	platform_set_drvdata(pdev, iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	 * Duplicate dai driver: depending on the slot masks configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	 * We'll change the number of channel provided by DAI stream, so dpcm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	 * channel merge can be done properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 			       sizeof(*dai_drv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	if (!dai_drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		       sizeof(*dai_drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	/* Bit clock provided on the pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	iface->sclk = devm_clk_get(dev, "sclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	if (IS_ERR(iface->sclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		ret = PTR_ERR(iface->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 			dev_err(dev, "failed to get sclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	/* Sample clock provided on the pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	iface->lrclk = devm_clk_get(dev, "lrclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	if (IS_ERR(iface->lrclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		ret = PTR_ERR(iface->lrclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 			dev_err(dev, "failed to get lrclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	 * mclk maybe be missing when the cpu dai is in slave mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	 * the codec does not require it to provide a master clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	 * At this point, ignore the error if mclk is missing. We'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	 * throw an error if the cpu dai is master and mclk is missing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	iface->mclk = devm_clk_get(dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	if (IS_ERR(iface->mclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		ret = PTR_ERR(iface->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		if (ret == -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 			iface->mclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 			if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 				dev_err(dev, "failed to get mclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	return devm_snd_soc_register_component(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 					&axg_tdm_iface_component_drv, dai_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 					ARRAY_SIZE(axg_tdm_iface_dai_drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static struct platform_driver axg_tdm_iface_pdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	.probe = axg_tdm_iface_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		.name = "axg-tdm-iface",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		.of_match_table = axg_tdm_iface_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) module_platform_driver(axg_tdm_iface_pdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_LICENSE("GPL v2");