^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/pcm_iec958.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The meaning of bits SPDIFOUT_CTRL0_XXX_SEL is actually the opposite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * of what the documentation says. Manual control on V, U and C bits is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * applied when the related sel bits are cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPDIFOUT_STAT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPDIFOUT_GAIN0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPDIFOUT_GAIN1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPDIFOUT_CTRL0 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPDIFOUT_CTRL0_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPDIFOUT_CTRL0_RST_OUT BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPDIFOUT_CTRL0_RST_IN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPDIFOUT_CTRL0_USEL BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPDIFOUT_CTRL0_USET BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPDIFOUT_CTRL0_CHSTS_SEL BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPDIFOUT_CTRL0_DATA_SEL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPDIFOUT_CTRL0_MSB_FIRST BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPDIFOUT_CTRL0_VSEL BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPDIFOUT_CTRL0_VSET BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPDIFOUT_CTRL0_MASK_MASK GENMASK(11, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPDIFOUT_CTRL0_MASK(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPDIFOUT_CTRL1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPDIFOUT_CTRL1_MSB_POS_MASK GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPDIFOUT_CTRL1_MSB_POS(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPDIFOUT_CTRL1_TYPE_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPDIFOUT_CTRL1_TYPE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPDIFOUT_PREAMB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPDIFOUT_SWAP 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPDIFOUT_CHSTS0 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPDIFOUT_CHSTS1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPDIFOUT_CHSTS2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPDIFOUT_CHSTS3 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPDIFOUT_CHSTS4 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPDIFOUT_CHSTS5 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPDIFOUT_CHSTS6 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPDIFOUT_CHSTS7 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPDIFOUT_CHSTS8 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPDIFOUT_CHSTS9 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPDIFOUT_CHSTSA 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPDIFOUT_CHSTSB 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPDIFOUT_MUTE_VAL 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct axg_spdifout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void axg_spdifout_enable(struct regmap *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Apply both reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) regmap_update_bits(map, SPDIFOUT_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SPDIFOUT_CTRL0_RST_OUT | SPDIFOUT_CTRL0_RST_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Clear out reset before in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) regmap_update_bits(map, SPDIFOUT_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SPDIFOUT_CTRL0_RST_OUT, SPDIFOUT_CTRL0_RST_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) regmap_update_bits(map, SPDIFOUT_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SPDIFOUT_CTRL0_RST_IN, SPDIFOUT_CTRL0_RST_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Enable spdifout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) regmap_update_bits(map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SPDIFOUT_CTRL0_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void axg_spdifout_disable(struct regmap *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) regmap_update_bits(map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int axg_spdifout_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) axg_spdifout_enable(priv->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) axg_spdifout_disable(priv->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int axg_spdifout_mute(struct snd_soc_dai *dai, int mute, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Use spdif valid bit to perform digital mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) regmap_update_bits(priv->map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_VSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mute ? SPDIFOUT_CTRL0_VSET : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int axg_spdifout_sample_fmt(struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Set the samples spdifout will pull from the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) switch (params_channels(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val = SPDIFOUT_CTRL0_MASK(0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) val = SPDIFOUT_CTRL0_MASK(0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(dai->dev, "too many channels for spdif dai: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) params_channels(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) regmap_update_bits(priv->map, SPDIFOUT_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SPDIFOUT_CTRL0_MASK_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* FIFO data are arranged in chunks of 64bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) switch (params_physical_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* 8 samples of 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val = SPDIFOUT_CTRL1_TYPE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* 4 samples of 16 bits - right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val = SPDIFOUT_CTRL1_TYPE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* 2 samples of 32 bits - right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val = SPDIFOUT_CTRL1_TYPE(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(dai->dev, "Unsupported physical width: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) params_physical_width(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Position of the MSB in FIFO samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) val |= SPDIFOUT_CTRL1_MSB_POS(params_width(params) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) regmap_update_bits(priv->map, SPDIFOUT_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SPDIFOUT_CTRL1_MSB_POS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SPDIFOUT_CTRL1_TYPE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) regmap_update_bits(priv->map, SPDIFOUT_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SPDIFOUT_CTRL0_MSB_FIRST | SPDIFOUT_CTRL0_DATA_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int axg_spdifout_set_chsts(struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 cs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = snd_pcm_create_iec958_consumer_hw_params(params, cs, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(dai->dev, "Creating IEC958 channel status failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val = cs[0] | cs[1] << 8 | cs[2] << 16 | cs[3] << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Setup channel status A bits [31 - 0]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) regmap_write(priv->map, SPDIFOUT_CHSTS0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Clear channel status A bits [191 - 32] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (offset = SPDIFOUT_CHSTS1; offset <= SPDIFOUT_CHSTS5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) offset += regmap_get_reg_stride(priv->map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) regmap_write(priv->map, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Setup channel status B bits [31 - 0]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) regmap_write(priv->map, SPDIFOUT_CHSTS6, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Clear channel status B bits [191 - 32] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (offset = SPDIFOUT_CHSTS7; offset <= SPDIFOUT_CHSTSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) offset += regmap_get_reg_stride(priv->map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regmap_write(priv->map, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int axg_spdifout_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* 2 * 32bits per subframe * 2 channels = 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = clk_set_rate(priv->mclk, rate * 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_err(dai->dev, "failed to set spdif clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = axg_spdifout_sample_fmt(params, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(dai->dev, "failed to setup sample format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = axg_spdifout_set_chsts(params, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dai->dev, "failed to setup channel status words\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int axg_spdifout_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Clock the spdif output block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = clk_prepare_enable(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(dai->dev, "failed to enable pclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Make sure the block is initially stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) axg_spdifout_disable(priv->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Insert data from bit 27 lsb first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) regmap_update_bits(priv->map, SPDIFOUT_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SPDIFOUT_CTRL0_MSB_FIRST | SPDIFOUT_CTRL0_DATA_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Manual control of V, C and U, U = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) regmap_update_bits(priv->map, SPDIFOUT_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SPDIFOUT_CTRL0_CHSTS_SEL | SPDIFOUT_CTRL0_VSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SPDIFOUT_CTRL0_USEL | SPDIFOUT_CTRL0_USET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Static SWAP configuration ATM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) regmap_write(priv->map, SPDIFOUT_SWAP, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void axg_spdifout_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct axg_spdifout *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk_disable_unprepare(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct snd_soc_dai_ops axg_spdifout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .trigger = axg_spdifout_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .mute_stream = axg_spdifout_mute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .hw_params = axg_spdifout_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .startup = axg_spdifout_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .shutdown = axg_spdifout_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .no_capture_mute = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static struct snd_soc_dai_driver axg_spdifout_dai_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = "SPDIF Output",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .stream_name = "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .rates = (SNDRV_PCM_RATE_32000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SNDRV_PCM_RATE_96000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) SNDRV_PCM_RATE_176400 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SNDRV_PCM_RATE_192000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .formats = (SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) SNDRV_PCM_FMTBIT_S20_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SNDRV_PCM_FMTBIT_S24_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .ops = &axg_spdifout_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const char * const spdifout_sel_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "IN 0", "IN 1", "IN 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static SOC_ENUM_SINGLE_DECL(axg_spdifout_sel_enum, SPDIFOUT_CTRL1, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) spdifout_sel_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct snd_kcontrol_new axg_spdifout_in_mux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SOC_DAPM_ENUM("Input Source", axg_spdifout_sel_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const struct snd_soc_dapm_widget axg_spdifout_dapm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_spdifout_in_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct snd_soc_dapm_route axg_spdifout_dapm_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { "SRC SEL", "IN 0", "IN 0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { "SRC SEL", "IN 1", "IN 1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { "SRC SEL", "IN 2", "IN 2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { "Playback", NULL, "SRC SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct snd_kcontrol_new axg_spdifout_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SOC_DOUBLE("Playback Volume", SPDIFOUT_GAIN0, 0, 8, 255, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) SOC_DOUBLE("Playback Switch", SPDIFOUT_CTRL0, 22, 21, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SOC_SINGLE("Playback Gain Enable Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SPDIFOUT_CTRL1, 26, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SOC_SINGLE("Playback Channels Mix Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SPDIFOUT_CTRL0, 23, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int axg_spdifout_set_bias_level(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) enum snd_soc_bias_level level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct axg_spdifout *priv = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) enum snd_soc_bias_level now =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) snd_soc_component_get_bias_level(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) switch (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case SND_SOC_BIAS_PREPARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (now == SND_SOC_BIAS_STANDBY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = clk_prepare_enable(priv->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case SND_SOC_BIAS_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (now == SND_SOC_BIAS_PREPARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) clk_disable_unprepare(priv->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case SND_SOC_BIAS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case SND_SOC_BIAS_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const struct snd_soc_component_driver axg_spdifout_component_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .controls = axg_spdifout_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .num_controls = ARRAY_SIZE(axg_spdifout_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .dapm_widgets = axg_spdifout_dapm_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .num_dapm_widgets = ARRAY_SIZE(axg_spdifout_dapm_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .dapm_routes = axg_spdifout_dapm_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .num_dapm_routes = ARRAY_SIZE(axg_spdifout_dapm_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .set_bias_level = axg_spdifout_set_bias_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct regmap_config axg_spdifout_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .max_register = SPDIFOUT_MUTE_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct of_device_id axg_spdifout_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { .compatible = "amlogic,axg-spdifout", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_DEVICE_TABLE(of, axg_spdifout_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int axg_spdifout_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct axg_spdifout *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) priv->map = devm_regmap_init_mmio(dev, regs, &axg_spdifout_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (IS_ERR(priv->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(dev, "failed to init regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PTR_ERR(priv->map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return PTR_ERR(priv->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) priv->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (IS_ERR(priv->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = PTR_ERR(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(dev, "failed to get pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) priv->mclk = devm_clk_get(dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (IS_ERR(priv->mclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = PTR_ERR(priv->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(dev, "failed to get mclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return devm_snd_soc_register_component(dev, &axg_spdifout_component_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) axg_spdifout_dai_drv, ARRAY_SIZE(axg_spdifout_dai_drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct platform_driver axg_spdifout_pdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .probe = axg_spdifout_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .name = "axg-spdifout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .of_match_table = axg_spdifout_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) module_platform_driver(axg_spdifout_pdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_DESCRIPTION("Amlogic AXG SPDIF Output driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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