^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SPDIFIN_CTRL0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPDIFIN_CTRL0_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPDIFIN_CTRL0_RST_OUT BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPDIFIN_CTRL0_RST_IN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPDIFIN_CTRL0_WIDTH_SEL BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPDIFIN_CTRL0_STATUS_CH_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPDIFIN_CTRL0_STATUS_SEL GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPDIFIN_CTRL0_SRC_SEL GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPDIFIN_CTRL0_CHK_VALID BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPDIFIN_CTRL1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPDIFIN_CTRL1_BASE_TIMER GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPDIFIN_CTRL1_IRQ_MASK GENMASK(27, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPDIFIN_CTRL2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPDIFIN_THRES_PER_REG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPDIFIN_THRES_WIDTH 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPDIFIN_CTRL3 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPDIFIN_CTRL4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPDIFIN_TIMER_PER_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPDIFIN_TIMER_WIDTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPDIFIN_CTRL5 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPDIFIN_CTRL6 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPDIFIN_STAT0 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPDIFIN_STAT0_MODE GENMASK(30, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPDIFIN_STAT0_MAXW GENMASK(17, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPDIFIN_STAT0_IRQ GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPDIFIN_IRQ_MODE_CHANGED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPDIFIN_STAT1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPDIFIN_STAT2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPDIFIN_MUTE_VAL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPDIFIN_MODE_NUM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct axg_spdifin_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const unsigned int *mode_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct axg_spdifin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const struct axg_spdifin_cfg *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * It would have been nice to check the actual rate against the sample rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * requested in hw_params(). Unfortunately, I was not able to make the mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * detection and IRQ work reliably:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 1. IRQs are generated on mode change only, so there is no notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * on transition between no signal and mode 0 (32kHz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 2. Mode detection very often has glitches, and may detects the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * lowest or the highest mode before zeroing in on the actual mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * This makes calling snd_pcm_stop() difficult to get right. Even notifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * the kcontrol would be very unreliable at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Let's keep things simple until the magic spell that makes this work is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static unsigned int axg_spdifin_get_rate(struct axg_spdifin *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int stat, mode, rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) regmap_read(priv->map, SPDIFIN_STAT0, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mode = FIELD_GET(SPDIFIN_STAT0_MODE, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * If max width is zero, we are not capturing anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Also Sometimes, when the capture is on but there is no data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * mode is SPDIFIN_MODE_NUM, but not always ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (FIELD_GET(SPDIFIN_STAT0_MAXW, stat) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mode < SPDIFIN_MODE_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rate = priv->conf->mode_rates[mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int axg_spdifin_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Apply both reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regmap_update_bits(priv->map, SPDIFIN_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SPDIFIN_CTRL0_RST_OUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SPDIFIN_CTRL0_RST_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Clear out reset before in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) regmap_update_bits(priv->map, SPDIFIN_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SPDIFIN_CTRL0_RST_OUT, SPDIFIN_CTRL0_RST_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regmap_update_bits(priv->map, SPDIFIN_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SPDIFIN_CTRL0_RST_IN, SPDIFIN_CTRL0_RST_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int axg_spdifin_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = clk_prepare_enable(priv->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_err(dai->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "failed to enable spdifin reference clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SPDIFIN_CTRL0_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void axg_spdifin_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clk_disable_unprepare(priv->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void axg_spdifin_write_mode_param(struct regmap *map, int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int num_per_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int base_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) uint64_t offset = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int reg, shift, rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) rem = do_div(offset, num_per_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) reg = offset * regmap_get_reg_stride(map) + base_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) shift = width * (num_per_reg - 1 - rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void axg_spdifin_write_timer(struct regmap *map, int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_TIMER_PER_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SPDIFIN_CTRL4, SPDIFIN_TIMER_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void axg_spdifin_write_threshold(struct regmap *map, int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_THRES_PER_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SPDIFIN_CTRL2, SPDIFIN_THRES_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static unsigned int axg_spdifin_mode_timer(struct axg_spdifin *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Number of period of the reference clock during a period of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * input signal reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return rate / (128 * priv->conf->mode_rates[mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct axg_spdifin *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int rate, t_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int ret, i = SPDIFIN_MODE_NUM - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Set spdif input reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = clk_set_rate(priv->refclk, priv->conf->ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(dai->dev, "reference clock rate set failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * The rate actually set might be slightly different, get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * the actual rate for the following mode calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rate = clk_get_rate(priv->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* HW will update mode every 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) regmap_update_bits(priv->map, SPDIFIN_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SPDIFIN_CTRL1_BASE_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FIELD_PREP(SPDIFIN_CTRL1_BASE_TIMER, rate / 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Threshold based on the minimum width between two edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) regmap_update_bits(priv->map, SPDIFIN_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SPDIFIN_CTRL0_WIDTH_SEL, SPDIFIN_CTRL0_WIDTH_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Calculate the last timer which has no threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) t_next = axg_spdifin_mode_timer(priv, i, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) axg_spdifin_write_timer(priv->map, i, t_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) i -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Calculate the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) t = axg_spdifin_mode_timer(priv, i, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Set the timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) axg_spdifin_write_timer(priv->map, i, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Set the threshold value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) axg_spdifin_write_threshold(priv->map, i, t + t_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Save the current timer for the next threshold calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) t_next = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } while (i > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int axg_spdifin_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = clk_prepare_enable(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(dai->dev, "failed to enable pclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = axg_spdifin_sample_mode_config(dai, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(dai->dev, "mode configuration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clk_disable_unprepare(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int axg_spdifin_dai_remove(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clk_disable_unprepare(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct snd_soc_dai_ops axg_spdifin_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .prepare = axg_spdifin_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .startup = axg_spdifin_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .shutdown = axg_spdifin_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int axg_spdifin_iec958_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int axg_spdifin_get_status_mask(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < 24; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ucontrol->value.iec958.status[i] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int axg_spdifin_get_status(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) regmap_update_bits(priv->map, SPDIFIN_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SPDIFIN_CTRL0_STATUS_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) FIELD_PREP(SPDIFIN_CTRL0_STATUS_SEL, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regmap_read(priv->map, SPDIFIN_STAT1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int offset = i * 4 + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ucontrol->value.iec958.status[offset] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) (val >> (j * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define AXG_SPDIFIN_IEC958_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .access = SNDRV_CTL_ELEM_ACCESS_READ, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .info = axg_spdifin_iec958_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .get = axg_spdifin_get_status_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define AXG_SPDIFIN_IEC958_STATUS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .access = (SNDRV_CTL_ELEM_ACCESS_READ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SNDRV_CTL_ELEM_ACCESS_VOLATILE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .info = axg_spdifin_iec958_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .get = axg_spdifin_get_status, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const char * const spdifin_chsts_src_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "A", "B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static SOC_ENUM_SINGLE_DECL(axg_spdifin_chsts_src_enum, SPDIFIN_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SPDIFIN_CTRL0_STATUS_CH_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) spdifin_chsts_src_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int axg_spdifin_rate_lock_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) uinfo->value.integer.max = 192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int axg_spdifin_rate_lock_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ucontrol->value.integer.value[0] = axg_spdifin_get_rate(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define AXG_SPDIFIN_LOCK_RATE(xname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .access = (SNDRV_CTL_ELEM_ACCESS_READ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) SNDRV_CTL_ELEM_ACCESS_VOLATILE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .get = axg_spdifin_rate_lock_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .info = axg_spdifin_rate_lock_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct snd_kcontrol_new axg_spdifin_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) AXG_SPDIFIN_LOCK_RATE("Capture Rate Lock"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SOC_DOUBLE("Capture Switch", SPDIFIN_CTRL0, 7, 6, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) SOC_ENUM(SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) axg_spdifin_chsts_src_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) AXG_SPDIFIN_IEC958_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) AXG_SPDIFIN_IEC958_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct snd_soc_component_driver axg_spdifin_component_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .controls = axg_spdifin_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .num_controls = ARRAY_SIZE(axg_spdifin_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct regmap_config axg_spdifin_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .max_register = SPDIFIN_MUTE_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const unsigned int axg_spdifin_mode_rates[SPDIFIN_MODE_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 32000, 44100, 48000, 88200, 96000, 176400, 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct axg_spdifin_cfg axg_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .mode_rates = axg_spdifin_mode_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .ref_rate = 333333333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct of_device_id axg_spdifin_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .compatible = "amlogic,axg-spdifin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .data = &axg_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }, {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_DEVICE_TABLE(of, axg_spdifin_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct snd_soc_dai_driver *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) axg_spdifin_get_dai_drv(struct device *dev, struct axg_spdifin *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct snd_soc_dai_driver *drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) drv->name = "SPDIF Input";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) drv->ops = &axg_spdifin_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) drv->probe = axg_spdifin_dai_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) drv->remove = axg_spdifin_dai_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) drv->capture.stream_name = "Capture";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) drv->capture.channels_min = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) drv->capture.channels_max = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) drv->capture.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) for (i = 0; i < SPDIFIN_MODE_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned int rb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) snd_pcm_rate_to_rate_bit(priv->conf->mode_rates[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (rb == SNDRV_PCM_RATE_KNOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) drv->capture.rates |= rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int axg_spdifin_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct axg_spdifin *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct snd_soc_dai_driver *dai_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) priv->conf = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!priv->conf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(dev, "failed to match device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) priv->map = devm_regmap_init_mmio(dev, regs, &axg_spdifin_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (IS_ERR(priv->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_err(dev, "failed to init regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PTR_ERR(priv->map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return PTR_ERR(priv->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) priv->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (IS_ERR(priv->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = PTR_ERR(priv->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(dev, "failed to get pclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) priv->refclk = devm_clk_get(dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (IS_ERR(priv->refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = PTR_ERR(priv->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_err(dev, "failed to get mclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dai_drv = axg_spdifin_get_dai_drv(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (IS_ERR(dai_drv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(dev, "failed to get dai driver: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PTR_ERR(dai_drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return PTR_ERR(dai_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return devm_snd_soc_register_component(dev, &axg_spdifin_component_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dai_drv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static struct platform_driver axg_spdifin_pdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .probe = axg_spdifin_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = "axg-spdifin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .of_match_table = axg_spdifin_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) module_platform_driver(axg_spdifin_pdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MODULE_DESCRIPTION("Amlogic AXG SPDIF Input driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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