^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This driver implements the frontend playback DAI of AXG and G12A based SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "axg-fifo.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CTRL0_FRDDR_PP_MODE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CTRL0_SEL1_EN_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CTRL0_SEL2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CTRL0_SEL2_EN_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CTRL0_SEL3_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CTRL0_SEL3_EN_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CTRL1_FRDDR_FORCE_FINISH BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CTRL2_SEL1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CTRL2_SEL1_EN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CTRL2_SEL2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CTRL2_SEL2_EN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CTRL2_SEL3_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CTRL2_SEL3_EN_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int g12a_frddr_dai_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Reset the read pointer to the FIFO_INIT_ADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) regmap_update_bits(fifo->map, FIFO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CTRL1_FRDDR_FORCE_FINISH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) regmap_update_bits(fifo->map, FIFO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CTRL1_FRDDR_FORCE_FINISH, CTRL1_FRDDR_FORCE_FINISH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) regmap_update_bits(fifo->map, FIFO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CTRL1_FRDDR_FORCE_FINISH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int axg_frddr_dai_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Enable pclk to access registers and clock the fifo ip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ret = clk_prepare_enable(fifo->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Apply single buffer mode to the interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Use all fifo depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) val = (fifo->depth / AXG_FIFO_BURST) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CTRL1_FRDDR_DEPTH(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void axg_frddr_dai_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clk_disable_unprepare(fifo->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int axg_frddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct snd_soc_dai_ops axg_frddr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .startup = axg_frddr_dai_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .shutdown = axg_frddr_dai_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct snd_soc_dai_driver axg_frddr_dai_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .name = "FRDDR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .stream_name = "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .channels_max = AXG_FIFO_CH_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .rates = AXG_FIFO_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .formats = AXG_FIFO_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .ops = &axg_frddr_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .pcm_new = axg_frddr_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char * const axg_frddr_sel_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "OUT 0", "OUT 1", "OUT 2", "OUT 3", "OUT 4", "OUT 5", "OUT 6", "OUT 7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static SOC_ENUM_SINGLE_DECL(axg_frddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) axg_frddr_sel_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct snd_kcontrol_new axg_frddr_out_demux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SOC_DAPM_ENUM("Output Sink", axg_frddr_sel_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct snd_soc_dapm_widget axg_frddr_dapm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SND_SOC_DAPM_DEMUX("SINK SEL", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) &axg_frddr_out_demux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct snd_soc_dapm_route axg_frddr_dapm_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { "SINK SEL", NULL, "Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { "OUT 0", "OUT 0", "SINK SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { "OUT 1", "OUT 1", "SINK SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { "OUT 2", "OUT 2", "SINK SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { "OUT 3", "OUT 3", "SINK SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { "OUT 4", "OUT 4", "SINK SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { "OUT 5", "OUT 5", "SINK SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { "OUT 6", "OUT 6", "SINK SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { "OUT 7", "OUT 7", "SINK SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct snd_soc_component_driver axg_frddr_component_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .dapm_widgets = axg_frddr_dapm_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .num_dapm_widgets = ARRAY_SIZE(axg_frddr_dapm_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .dapm_routes = axg_frddr_dapm_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .num_dapm_routes = ARRAY_SIZE(axg_frddr_dapm_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .open = axg_fifo_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .close = axg_fifo_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .hw_params = axg_fifo_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .hw_free = axg_fifo_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .pointer = axg_fifo_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .trigger = axg_fifo_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct axg_fifo_match_data axg_frddr_match_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .component_drv = &axg_frddr_component_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .dai_drv = &axg_frddr_dai_drv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct snd_soc_dai_ops g12a_frddr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .prepare = g12a_frddr_dai_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .startup = axg_frddr_dai_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .shutdown = axg_frddr_dai_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct snd_soc_dai_driver g12a_frddr_dai_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "FRDDR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .stream_name = "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .channels_max = AXG_FIFO_CH_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .rates = AXG_FIFO_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .formats = AXG_FIFO_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .ops = &g12a_frddr_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .pcm_new = axg_frddr_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel1_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) axg_frddr_sel_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel2_enum, FIFO_CTRL0, CTRL0_SEL2_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) axg_frddr_sel_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel3_enum, FIFO_CTRL0, CTRL0_SEL3_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) axg_frddr_sel_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct snd_kcontrol_new g12a_frddr_out1_demux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SOC_DAPM_ENUM("Output Src 1", g12a_frddr_sel1_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct snd_kcontrol_new g12a_frddr_out2_demux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SOC_DAPM_ENUM("Output Src 2", g12a_frddr_sel2_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct snd_kcontrol_new g12a_frddr_out3_demux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SOC_DAPM_ENUM("Output Src 3", g12a_frddr_sel3_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct snd_kcontrol_new g12a_frddr_out1_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CTRL0_SEL1_EN_SHIFT, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct snd_kcontrol_new g12a_frddr_out2_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CTRL0_SEL2_EN_SHIFT, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct snd_kcontrol_new g12a_frddr_out3_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CTRL0_SEL3_EN_SHIFT, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct snd_soc_dapm_widget g12a_frddr_dapm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) &g12a_frddr_out1_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) &g12a_frddr_out2_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) &g12a_frddr_out3_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) &g12a_frddr_out1_demux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) &g12a_frddr_out2_demux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &g12a_frddr_out3_demux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct snd_soc_dapm_route g12a_frddr_dapm_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { "SRC 1", NULL, "Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { "SRC 2", NULL, "Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { "SRC 3", NULL, "Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { "SRC 1 EN", "Switch", "SRC 1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { "SRC 2 EN", "Switch", "SRC 2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { "SRC 3 EN", "Switch", "SRC 3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { "SINK 1 SEL", NULL, "SRC 1 EN" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { "SINK 2 SEL", NULL, "SRC 2 EN" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { "SINK 3 SEL", NULL, "SRC 3 EN" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { "OUT 0", "OUT 0", "SINK 1 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { "OUT 1", "OUT 1", "SINK 1 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { "OUT 2", "OUT 2", "SINK 1 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { "OUT 3", "OUT 3", "SINK 1 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { "OUT 4", "OUT 4", "SINK 1 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { "OUT 5", "OUT 5", "SINK 1 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { "OUT 6", "OUT 6", "SINK 1 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { "OUT 7", "OUT 7", "SINK 1 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { "OUT 0", "OUT 0", "SINK 2 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { "OUT 1", "OUT 1", "SINK 2 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { "OUT 2", "OUT 2", "SINK 2 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { "OUT 3", "OUT 3", "SINK 2 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { "OUT 4", "OUT 4", "SINK 2 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { "OUT 5", "OUT 5", "SINK 2 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { "OUT 6", "OUT 6", "SINK 2 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { "OUT 7", "OUT 7", "SINK 2 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { "OUT 0", "OUT 0", "SINK 3 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { "OUT 1", "OUT 1", "SINK 3 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { "OUT 2", "OUT 2", "SINK 3 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { "OUT 3", "OUT 3", "SINK 3 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { "OUT 4", "OUT 4", "SINK 3 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { "OUT 5", "OUT 5", "SINK 3 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { "OUT 6", "OUT 6", "SINK 3 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { "OUT 7", "OUT 7", "SINK 3 SEL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct snd_soc_component_driver g12a_frddr_component_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .dapm_widgets = g12a_frddr_dapm_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .num_dapm_widgets = ARRAY_SIZE(g12a_frddr_dapm_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .dapm_routes = g12a_frddr_dapm_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .open = axg_fifo_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .close = axg_fifo_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .hw_params = g12a_fifo_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .hw_free = axg_fifo_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .pointer = axg_fifo_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .trigger = axg_fifo_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct axg_fifo_match_data g12a_frddr_match_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .component_drv = &g12a_frddr_component_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .dai_drv = &g12a_frddr_dai_drv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* On SM1, the output selection in on CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct snd_kcontrol_new sm1_frddr_out1_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CTRL2_SEL1_EN_SHIFT, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct snd_kcontrol_new sm1_frddr_out2_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) CTRL2_SEL2_EN_SHIFT, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct snd_kcontrol_new sm1_frddr_out3_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CTRL2_SEL3_EN_SHIFT, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel1_enum, FIFO_CTRL2, CTRL2_SEL1_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) axg_frddr_sel_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel2_enum, FIFO_CTRL2, CTRL2_SEL2_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) axg_frddr_sel_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static SOC_ENUM_SINGLE_DECL(sm1_frddr_sel3_enum, FIFO_CTRL2, CTRL2_SEL3_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) axg_frddr_sel_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct snd_kcontrol_new sm1_frddr_out1_demux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SOC_DAPM_ENUM("Output Src 1", sm1_frddr_sel1_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct snd_kcontrol_new sm1_frddr_out2_demux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SOC_DAPM_ENUM("Output Src 2", sm1_frddr_sel2_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct snd_kcontrol_new sm1_frddr_out3_demux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) SOC_DAPM_ENUM("Output Src 3", sm1_frddr_sel3_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct snd_soc_dapm_widget sm1_frddr_dapm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) &sm1_frddr_out1_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) &sm1_frddr_out2_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) &sm1_frddr_out3_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) &sm1_frddr_out1_demux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) &sm1_frddr_out2_demux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) &sm1_frddr_out3_demux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SND_SOC_DAPM_AIF_OUT("OUT 5", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SND_SOC_DAPM_AIF_OUT("OUT 6", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SND_SOC_DAPM_AIF_OUT("OUT 7", NULL, 0, SND_SOC_NOPM, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct snd_soc_component_driver sm1_frddr_component_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .dapm_widgets = sm1_frddr_dapm_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .num_dapm_widgets = ARRAY_SIZE(sm1_frddr_dapm_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .dapm_routes = g12a_frddr_dapm_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .open = axg_fifo_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .close = axg_fifo_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .hw_params = g12a_fifo_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .hw_free = axg_fifo_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .pointer = axg_fifo_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .trigger = axg_fifo_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct axg_fifo_match_data sm1_frddr_match_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .component_drv = &sm1_frddr_component_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .dai_drv = &g12a_frddr_dai_drv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct of_device_id axg_frddr_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .compatible = "amlogic,axg-frddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .data = &axg_frddr_match_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .compatible = "amlogic,g12a-frddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .data = &g12a_frddr_match_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .compatible = "amlogic,sm1-frddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .data = &sm1_frddr_match_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }, {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_DEVICE_TABLE(of, axg_frddr_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static struct platform_driver axg_frddr_pdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .probe = axg_fifo_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = "axg-frddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .of_match_table = axg_frddr_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) module_platform_driver(axg_frddr_pdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MODULE_DESCRIPTION("Amlogic AXG/G12A playback fifo driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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