Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2018 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "axg-fifo.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * This file implements the platform operations common to the playback and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * capture frontend DAI. The logic behind this two types of fifo is very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * similar but some difference exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * These differences are handled in the respective DAI drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static struct snd_pcm_hardware axg_fifo_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	.info = (SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		 SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		 SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		 SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		 SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.formats = AXG_FIFO_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.rate_min = 5512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.channels_max = AXG_FIFO_CH_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.period_bytes_min = AXG_FIFO_BURST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	.period_bytes_max = UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.periods_max = UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	/* No real justification for this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.buffer_bytes_max = 1 * 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static struct snd_soc_dai *axg_fifo_dai(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct snd_soc_pcm_runtime *rtd = ss->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static struct axg_fifo *axg_fifo_data(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct snd_soc_dai *dai = axg_fifo_dai(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static struct device *axg_fifo_dev(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct snd_soc_dai *dai = axg_fifo_dai(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return dai->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static void __dma_enable(struct axg_fifo *fifo,  bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			   enable ? CTRL0_DMA_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) int axg_fifo_pcm_trigger(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			 struct snd_pcm_substream *ss, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct axg_fifo *fifo = axg_fifo_data(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		__dma_enable(fifo, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		__dma_enable(fifo, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) EXPORT_SYMBOL_GPL(axg_fifo_pcm_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				       struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct axg_fifo *fifo = axg_fifo_data(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct snd_pcm_runtime *runtime = ss->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	regmap_read(fifo->map, FIFO_STATUS2, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) EXPORT_SYMBOL_GPL(axg_fifo_pcm_pointer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			   struct snd_pcm_substream *ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			   struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct snd_pcm_runtime *runtime = ss->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct axg_fifo *fifo = axg_fifo_data(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	unsigned int burst_num, period, threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	dma_addr_t end_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	period = params_period_bytes(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* Setup dma memory pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* Setup interrupt periodicity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	burst_num = period / AXG_FIFO_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * Start the fifo request on the smallest of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 * - Half the fifo size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * - Half the period size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	threshold = min(period / 2, fifo->depth / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * With the threshold in bytes, register value is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * V = (threshold / burst) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	threshold /= AXG_FIFO_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	regmap_field_write(fifo->field_threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			   threshold ? threshold - 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/* Enable block count irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	regmap_update_bits(fifo->map, FIFO_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			   CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			   CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int g12a_fifo_pcm_hw_params(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			    struct snd_pcm_substream *ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			    struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct axg_fifo *fifo = axg_fifo_data(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct snd_pcm_runtime *runtime = ss->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ret = axg_fifo_pcm_hw_params(component, ss, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* Set the initial memory address of the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) EXPORT_SYMBOL_GPL(g12a_fifo_pcm_hw_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			 struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct axg_fifo *fifo = axg_fifo_data(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* Disable the block count irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	regmap_update_bits(fifo->map, FIFO_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			   CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	regmap_update_bits(fifo->map, FIFO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			   CTRL1_INT_CLR(FIFO_INT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			   CTRL1_INT_CLR(mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* Clear must also be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	regmap_update_bits(fifo->map, FIFO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			   CTRL1_INT_CLR(FIFO_INT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			   0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct snd_pcm_substream *ss = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct axg_fifo *fifo = axg_fifo_data(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	regmap_read(fifo->map, FIFO_STATUS1, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	status = STATUS1_INT_STS(status) & FIFO_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (status & FIFO_INT_COUNT_REPEAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		snd_pcm_period_elapsed(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* Ack irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	axg_fifo_ack_irq(fifo, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return IRQ_RETVAL(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int axg_fifo_pcm_open(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		      struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct axg_fifo *fifo = axg_fifo_data(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct device *dev = axg_fifo_dev(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	snd_soc_set_runtime_hwparams(ss, &axg_fifo_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * Make sure the buffer and period size are multiple of the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 					 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					 AXG_FIFO_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret = snd_pcm_hw_constraint_step(ss->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 					 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 					 AXG_FIFO_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			  dev_name(dev), ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* Enable pclk to access registers and clock the fifo ip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ret = clk_prepare_enable(fifo->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		goto free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* Setup status2 so it reports the memory pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	regmap_update_bits(fifo->map, FIFO_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			   CTRL1_STATUS2_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			   CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* Make sure the dma is initially disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	__dma_enable(fifo, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* Disable irqs until params are ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	regmap_update_bits(fifo->map, FIFO_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			   CTRL0_INT_EN(FIFO_INT_MASK), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* Clear any pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* Take memory arbitror out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ret = reset_control_deassert(fifo->arb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		goto free_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) free_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	clk_disable_unprepare(fifo->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	free_irq(fifo->irq, ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) EXPORT_SYMBOL_GPL(axg_fifo_pcm_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int axg_fifo_pcm_close(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		       struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct axg_fifo *fifo = axg_fifo_data(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* Put the memory arbitror back in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ret = reset_control_assert(fifo->arb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* Disable fifo ip and register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	clk_disable_unprepare(fifo->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* remove IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	free_irq(fifo->irq, ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) EXPORT_SYMBOL_GPL(axg_fifo_pcm_close);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct snd_card *card = rtd->card->snd_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	size_t size = axg_fifo_hw.buffer_bytes_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	snd_pcm_set_managed_buffer(rtd->pcm->streams[type].substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				   SNDRV_DMA_TYPE_DEV, card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 				   size, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) EXPORT_SYMBOL_GPL(axg_fifo_pcm_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct regmap_config axg_fifo_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.reg_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.reg_stride	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.max_register	= FIFO_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int axg_fifo_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	const struct axg_fifo_match_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	struct axg_fifo *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		dev_err(dev, "failed to match device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (!fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	platform_set_drvdata(pdev, fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (IS_ERR(fifo->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		dev_err(dev, "failed to init regmap: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			PTR_ERR(fifo->map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		return PTR_ERR(fifo->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	fifo->pclk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (IS_ERR(fifo->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		if (PTR_ERR(fifo->pclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			dev_err(dev, "failed to get pclk: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 				PTR_ERR(fifo->pclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return PTR_ERR(fifo->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	fifo->arb = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (IS_ERR(fifo->arb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		if (PTR_ERR(fifo->arb) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			dev_err(dev, "failed to get arb reset: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 				PTR_ERR(fifo->arb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return PTR_ERR(fifo->arb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	fifo->irq = of_irq_get(dev->of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (fifo->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		dev_err(dev, "failed to get irq: %d\n", fifo->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		return fifo->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	fifo->field_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (IS_ERR(fifo->field_threshold))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return PTR_ERR(fifo->field_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 				   &fifo->depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		/* Error out for anything but a missing property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		if (ret != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		 * If the property is missing, it might be because of an old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		 * DT. In such case, assume the smallest known fifo depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		fifo->depth = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		dev_warn(dev, "fifo depth not found, assume %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			 fifo->depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return devm_snd_soc_register_component(dev, data->component_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 					       data->dai_drv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) EXPORT_SYMBOL_GPL(axg_fifo_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_LICENSE("GPL v2");