^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2020 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "aiu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "aiu-fifo.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AIU_IEC958_DCU_FF_CTRL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AIU_IEC958_DCU_FF_CTRL_AUTO_DISABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AIU_IEC958_DCU_FF_CTRL_IRQ_MODE GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AIU_IEC958_DCU_FF_CTRL_IRQ_OUT_THD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AIU_IEC958_DCU_FF_CTRL_IRQ_FRAME_READ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AIU_IEC958_DCU_FF_CTRL_SYNC_HEAD_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AIU_IEC958_DCU_FF_CTRL_BYTE_SEEK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AIU_IEC958_DCU_FF_CTRL_CONTINUE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AIU_MEM_IEC958_CONTROL_ENDIAN GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AIU_MEM_IEC958_CONTROL_RD_DDR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AIU_MEM_IEC958_CONTROL_MODE_16BIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AIU_MEM_IEC958_CONTROL_MODE_LINEAR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AIU_MEM_IEC958_BUF_CNTL_INIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AIU_FIFO_SPDIF_BLOCK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct snd_pcm_hardware fifo_spdif_pcm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .info = (SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .formats = AIU_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .rate_min = 5512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .period_bytes_min = AIU_FIFO_SPDIF_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .period_bytes_max = AIU_FIFO_SPDIF_BLOCK * USHRT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .periods_max = UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* No real justification for this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .buffer_bytes_max = 1 * 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void fifo_spdif_dcu_enable(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) snd_soc_component_update_bits(component, AIU_IEC958_DCU_FF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) AIU_IEC958_DCU_FF_CTRL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enable ? AIU_IEC958_DCU_FF_CTRL_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int fifo_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = aiu_fifo_trigger(substream, cmd, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) fifo_spdif_dcu_enable(component, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) fifo_spdif_dcu_enable(component, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int fifo_spdif_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = aiu_fifo_prepare(substream, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) snd_soc_component_update_bits(component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) AIU_MEM_IEC958_BUF_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) AIU_MEM_IEC958_BUF_CNTL_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) AIU_MEM_IEC958_BUF_CNTL_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) snd_soc_component_update_bits(component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) AIU_MEM_IEC958_BUF_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) AIU_MEM_IEC958_BUF_CNTL_INIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int fifo_spdif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = aiu_fifo_hw_params(substream, params, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val = AIU_MEM_IEC958_CONTROL_RD_DDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) AIU_MEM_IEC958_CONTROL_MODE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) switch (params_physical_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val |= AIU_MEM_IEC958_CONTROL_MODE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_err(dai->dev, "Unsupported physical width %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) params_physical_width(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) snd_soc_component_update_bits(component, AIU_MEM_IEC958_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) AIU_MEM_IEC958_CONTROL_ENDIAN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) AIU_MEM_IEC958_CONTROL_RD_DDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) AIU_MEM_IEC958_CONTROL_MODE_LINEAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) AIU_MEM_IEC958_CONTROL_MODE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Number bytes read by the FIFO between each IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) snd_soc_component_write(component, AIU_IEC958_BPF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) params_period_bytes(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * AUTO_DISABLE and SYNC_HEAD are enabled by default but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * this should be disabled in PCM (uncompressed) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) snd_soc_component_update_bits(component, AIU_IEC958_DCU_FF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) AIU_IEC958_DCU_FF_CTRL_AUTO_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) AIU_IEC958_DCU_FF_CTRL_IRQ_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) AIU_IEC958_DCU_FF_CTRL_SYNC_HEAD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) AIU_IEC958_DCU_FF_CTRL_IRQ_FRAME_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const struct snd_soc_dai_ops aiu_fifo_spdif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .trigger = fifo_spdif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .prepare = fifo_spdif_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .hw_params = fifo_spdif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .hw_free = aiu_fifo_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .startup = aiu_fifo_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .shutdown = aiu_fifo_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int aiu_fifo_spdif_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct aiu *aiu = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct aiu_fifo *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = aiu_fifo_dai_probe(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) fifo = dai->playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) fifo->pcm = &fifo_spdif_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) fifo->mem_offset = AIU_MEM_IEC958_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) fifo->fifo_block = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) fifo->pclk = aiu->spdif.clks[PCLK].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) fifo->irq = aiu->spdif.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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