^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2020 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "aiu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "aiu-fifo.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AIU_MEM_I2S_MASKS_IRQ_BLOCK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AIU_MEM_I2S_CONTROL_MODE_16BIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AIU_MEM_I2S_BUF_CNTL_INIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AIU_RST_SOFT_I2S_FAST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AIU_I2S_MISC_HOLD_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AIU_I2S_MISC_FORCE_LEFT_RIGHT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AIU_FIFO_I2S_BLOCK 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct snd_pcm_hardware fifo_i2s_pcm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .info = (SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SNDRV_PCM_INFO_PAUSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .formats = AIU_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .rate_min = 5512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .period_bytes_min = AIU_FIFO_I2S_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .period_bytes_max = AIU_FIFO_I2S_BLOCK * USHRT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .periods_max = UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* No real justification for this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .buffer_bytes_max = 1 * 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int aiu_fifo_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) snd_soc_component_write(component, AIU_RST_SOFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) AIU_RST_SOFT_I2S_FAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) snd_soc_component_read(component, AIU_I2S_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return aiu_fifo_trigger(substream, cmd, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int aiu_fifo_i2s_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ret = aiu_fifo_prepare(substream, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) snd_soc_component_update_bits(component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) AIU_MEM_I2S_BUF_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) AIU_MEM_I2S_BUF_CNTL_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) AIU_MEM_I2S_BUF_CNTL_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) snd_soc_component_update_bits(component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) AIU_MEM_I2S_BUF_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) AIU_MEM_I2S_BUF_CNTL_INIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int aiu_fifo_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct aiu_fifo *fifo = dai->playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) snd_soc_component_update_bits(component, AIU_I2S_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) AIU_I2S_MISC_HOLD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) AIU_I2S_MISC_HOLD_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = aiu_fifo_hw_params(substream, params, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) switch (params_physical_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val = AIU_MEM_I2S_CONTROL_MODE_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev_err(dai->dev, "Unsupported physical width %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) params_physical_width(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) snd_soc_component_update_bits(component, AIU_MEM_I2S_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) AIU_MEM_I2S_CONTROL_MODE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Setup the irq periodicity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val = params_period_bytes(params) / fifo->fifo_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) val = FIELD_PREP(AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) snd_soc_component_update_bits(component, AIU_MEM_I2S_MASKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Most (all?) supported SoCs have this bit set by default. The vendor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * driver however sets it manually (depending on the version either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * while un-setting AIU_I2S_MISC_HOLD_EN or right before that). Follow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * the same approach for consistency with the vendor driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) snd_soc_component_update_bits(component, AIU_I2S_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) AIU_I2S_MISC_FORCE_LEFT_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) AIU_I2S_MISC_FORCE_LEFT_RIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) snd_soc_component_update_bits(component, AIU_I2S_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) AIU_I2S_MISC_HOLD_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .trigger = aiu_fifo_i2s_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .prepare = aiu_fifo_i2s_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .hw_params = aiu_fifo_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .hw_free = aiu_fifo_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .startup = aiu_fifo_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .shutdown = aiu_fifo_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct aiu *aiu = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct aiu_fifo *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = aiu_fifo_dai_probe(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) fifo = dai->playback_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) fifo->pcm = &fifo_i2s_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) fifo->mem_offset = AIU_MEM_I2S_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) fifo->fifo_block = AIU_FIFO_I2S_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) fifo->pclk = aiu->i2s.clks[PCLK].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) fifo->irq = aiu->i2s.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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