^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2020 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/pcm_iec958.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "aiu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AIU_958_MISC_NON_PCM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AIU_958_MISC_MODE_16BITS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AIU_958_MISC_16BITS_ALIGN GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AIU_958_MISC_MODE_32BITS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AIU_958_MISC_U_FROM_STREAM BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AIU_958_MISC_FORCE_LR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AIU_958_CTRL_HOLD_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AIU_CLK_CTRL_958_DIV_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AIU_CLK_CTRL_958_DIV GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AIU_CLK_CTRL_958_DIV_MORE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AIU_CS_WORD_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AIU_958_INTERNAL_DIV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) aiu_encoder_spdif_divider_enable(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) snd_soc_component_update_bits(component, AIU_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) AIU_CLK_CTRL_958_DIV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enable ? AIU_CLK_CTRL_958_DIV_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void aiu_encoder_spdif_hold(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) snd_soc_component_update_bits(component, AIU_958_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) AIU_958_CTRL_HOLD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enable ? AIU_958_CTRL_HOLD_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) aiu_encoder_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) aiu_encoder_spdif_hold(component, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) aiu_encoder_spdif_hold(component, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int aiu_encoder_spdif_setup_cs_word(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 cs[AIU_CS_WORD_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = snd_pcm_create_iec958_consumer_hw_params(params, cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) AIU_CS_WORD_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Write the 1st half word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val = cs[1] | cs[0] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) snd_soc_component_write(component, AIU_958_CHSTAT_L0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) snd_soc_component_write(component, AIU_958_CHSTAT_R0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Write the 2nd half word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val = cs[3] | cs[2] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) snd_soc_component_write(component, AIU_958_CHSTAT_L1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) snd_soc_component_write(component, AIU_958_CHSTAT_R1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int aiu_encoder_spdif_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct aiu *aiu = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int val = 0, mrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Disable the clock while changing the settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) aiu_encoder_spdif_divider_enable(component, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (params_physical_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val |= AIU_958_MISC_MODE_16BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val |= FIELD_PREP(AIU_958_MISC_16BITS_ALIGN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val |= AIU_958_MISC_MODE_32BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_err(dai->dev, "Unsupport physical width\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) snd_soc_component_update_bits(component, AIU_958_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) AIU_958_MISC_NON_PCM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AIU_958_MISC_MODE_16BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) AIU_958_MISC_16BITS_ALIGN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AIU_958_MISC_MODE_32BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) AIU_958_MISC_FORCE_LR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) AIU_958_MISC_U_FROM_STREAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Set the stream channel status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = aiu_encoder_spdif_setup_cs_word(component, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_err(dai->dev, "failed to set channel status word\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) snd_soc_component_update_bits(component, AIU_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) AIU_CLK_CTRL_958_DIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) AIU_CLK_CTRL_958_DIV_MORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FIELD_PREP(AIU_CLK_CTRL_958_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __ffs(AIU_958_INTERNAL_DIV)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* 2 * 32bits per subframe * 2 channels = 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mrate = params_rate(params) * 128 * AIU_958_INTERNAL_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = clk_set_rate(aiu->spdif.clks[MCLK].clk, mrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(dai->dev, "failed to set mclk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) aiu_encoder_spdif_divider_enable(component, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int aiu_encoder_spdif_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) aiu_encoder_spdif_divider_enable(component, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int aiu_encoder_spdif_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * NOTE: Make sure the spdif block is on its own divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * The spdif can be clocked by the i2s master clock or its own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * clock. We should (in theory) change the source depending on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * origin of the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * However, considering the clocking scheme used on these platforms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * the master clocks will pick the same PLL source when they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * playing from the same FIFO. The clock should be in sync so, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * should not be necessary to reparent the spdif master clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = clk_set_parent(aiu->spdif.clks[MCLK].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) aiu->spdif_mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = clk_bulk_prepare_enable(aiu->spdif.clk_num, aiu->spdif.clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(dai->dev, "failed to enable spdif clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void aiu_encoder_spdif_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clk_bulk_disable_unprepare(aiu->spdif.clk_num, aiu->spdif.clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const struct snd_soc_dai_ops aiu_encoder_spdif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .trigger = aiu_encoder_spdif_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .hw_params = aiu_encoder_spdif_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .hw_free = aiu_encoder_spdif_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .startup = aiu_encoder_spdif_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .shutdown = aiu_encoder_spdif_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags