Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2020 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "aiu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define AIU_I2S_SOURCE_DESC_MODE_8CH	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AIU_I2S_SOURCE_DESC_MODE_24BIT	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define AIU_I2S_SOURCE_DESC_MODE_32BIT	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AIU_I2S_SOURCE_DESC_MODE_SPLIT	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AIU_RST_SOFT_I2S_FAST		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AIU_I2S_DAC_CFG_MSB_FIRST	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AIU_CLK_CTRL_I2S_DIV_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AIU_CLK_CTRL_I2S_DIV		GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AIU_CLK_CTRL_AOCLK_INVERT	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AIU_CLK_CTRL_LRCLK_INVERT	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AIU_CLK_CTRL_LRCLK_SKEW		GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AIU_CLK_CTRL_MORE_HDMI_AMCLK	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AIU_CLK_CTRL_MORE_I2S_DIV	GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AIU_CODEC_DAC_LRCLK_CTRL_DIV	GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static void aiu_encoder_i2s_divider_enable(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 					   bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	snd_soc_component_update_bits(component, AIU_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 				      AIU_CLK_CTRL_I2S_DIV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 				      enable ? AIU_CLK_CTRL_I2S_DIV_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static int aiu_encoder_i2s_setup_desc(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 				      struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	/* Always operate in split (classic interleaved) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	unsigned int desc = AIU_I2S_SOURCE_DESC_MODE_SPLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	/* Reset required to update the pipeline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	snd_soc_component_write(component, AIU_RST_SOFT, AIU_RST_SOFT_I2S_FAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	snd_soc_component_read(component, AIU_I2S_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	switch (params_physical_width(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	case 16: /* Nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		desc |= (AIU_I2S_SOURCE_DESC_MODE_24BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			 AIU_I2S_SOURCE_DESC_MODE_32BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	switch (params_channels(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case 2: /* Nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		desc |= AIU_I2S_SOURCE_DESC_MODE_8CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	snd_soc_component_update_bits(component, AIU_I2S_SOURCE_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 				      AIU_I2S_SOURCE_DESC_MODE_8CH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 				      AIU_I2S_SOURCE_DESC_MODE_24BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				      AIU_I2S_SOURCE_DESC_MODE_32BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				      AIU_I2S_SOURCE_DESC_MODE_SPLIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				      desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int aiu_encoder_i2s_set_legacy_div(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 					  struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 					  unsigned int bs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	switch (bs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		/* These are the only valid legacy dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		dev_err(component->dev, "Unsupported i2s divider: %u\n", bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	snd_soc_component_update_bits(component, AIU_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				      AIU_CLK_CTRL_I2S_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 				      FIELD_PREP(AIU_CLK_CTRL_I2S_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 						 __ffs(bs)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 				      AIU_CLK_CTRL_MORE_I2S_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				      FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 						 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int aiu_encoder_i2s_set_more_div(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 					struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					unsigned int bs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * NOTE: this HW is odd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * In most configuration, the i2s divider is 'mclk / blck'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * However, in 16 bits - 8ch mode, this factor needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * increased by 50% to get the correct output rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * No idea why !
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (params_width(params) == 16 && params_channels(params) == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		if (bs % 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			dev_err(component->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				"Cannot increase i2s divider by 50%%\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		bs += bs / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* Use CLK_MORE for mclk to bclk divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	snd_soc_component_update_bits(component, AIU_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				      AIU_CLK_CTRL_I2S_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				      FIELD_PREP(AIU_CLK_CTRL_I2S_DIV, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				      AIU_CLK_CTRL_MORE_I2S_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 				      FIELD_PREP(AIU_CLK_CTRL_MORE_I2S_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 						 bs - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int aiu_encoder_i2s_set_clocks(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				      struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct aiu *aiu = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned int srate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned int fs, bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* Get the oversampling factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (fs % 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Send data MSB first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	snd_soc_component_update_bits(component, AIU_I2S_DAC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				      AIU_I2S_DAC_CFG_MSB_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				      AIU_I2S_DAC_CFG_MSB_FIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* Set bclk to lrlck ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	snd_soc_component_update_bits(component, AIU_CODEC_DAC_LRCLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				      AIU_CODEC_DAC_LRCLK_CTRL_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				      FIELD_PREP(AIU_CODEC_DAC_LRCLK_CTRL_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 						 64 - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	bs = fs / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (aiu->platform->has_clk_ctrl_more_i2s_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		ret = aiu_encoder_i2s_set_more_div(component, params, bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		ret = aiu_encoder_i2s_set_legacy_div(component, params, bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* Make sure amclk is used for HDMI i2s as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	snd_soc_component_update_bits(component, AIU_CLK_CTRL_MORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				      AIU_CLK_CTRL_MORE_HDMI_AMCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				      AIU_CLK_CTRL_MORE_HDMI_AMCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int aiu_encoder_i2s_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				     struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				     struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* Disable the clock while changing the settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	aiu_encoder_i2s_divider_enable(component, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = aiu_encoder_i2s_setup_desc(component, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_err(dai->dev, "setting i2s desc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ret = aiu_encoder_i2s_set_clocks(component, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		dev_err(dai->dev, "setting i2s clocks failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	aiu_encoder_i2s_divider_enable(component, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int aiu_encoder_i2s_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				   struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	aiu_encoder_i2s_divider_enable(component, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int aiu_encoder_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct snd_soc_component *component = dai->component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	unsigned int inv = fmt & SND_SOC_DAIFMT_INV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned int skew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/* Only CPU Master / Codec Slave supported ATM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (inv == SND_SOC_DAIFMT_NB_IF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	    inv == SND_SOC_DAIFMT_IB_IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		val |= AIU_CLK_CTRL_LRCLK_INVERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (inv == SND_SOC_DAIFMT_IB_NF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	    inv == SND_SOC_DAIFMT_IB_IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		val |= AIU_CLK_CTRL_AOCLK_INVERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* Signal skew */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		/* Invert sample clock for i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		val ^= AIU_CLK_CTRL_LRCLK_INVERT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		skew = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	case SND_SOC_DAIFMT_LEFT_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		skew = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	val |= FIELD_PREP(AIU_CLK_CTRL_LRCLK_SKEW, skew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	snd_soc_component_update_bits(component, AIU_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				      AIU_CLK_CTRL_LRCLK_INVERT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				      AIU_CLK_CTRL_AOCLK_INVERT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				      AIU_CLK_CTRL_LRCLK_SKEW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				      val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int aiu_encoder_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				      unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (WARN_ON(clk_id != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (dir == SND_SOC_CLOCK_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		dev_err(dai->dev, "Failed to set sysclk to %uHz", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const unsigned int hw_channels[] = {2, 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct snd_pcm_hw_constraint_list hw_channel_constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.list = hw_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.count = ARRAY_SIZE(hw_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int aiu_encoder_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				   struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* Make sure the encoder gets either 2 or 8 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 					 SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 					 &hw_channel_constraints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		dev_err(dai->dev, "adding channels constraints failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ret = clk_bulk_prepare_enable(aiu->i2s.clk_num, aiu->i2s.clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		dev_err(dai->dev, "failed to enable i2s clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void aiu_encoder_i2s_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				     struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	clk_bulk_disable_unprepare(aiu->i2s.clk_num, aiu->i2s.clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.hw_params	= aiu_encoder_i2s_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.hw_free	= aiu_encoder_i2s_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.set_fmt	= aiu_encoder_i2s_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.set_sysclk	= aiu_encoder_i2s_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.startup	= aiu_encoder_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.shutdown	= aiu_encoder_i2s_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)