Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2020 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <sound/soc-dai.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <dt-bindings/sound/meson-aiu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "aiu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "meson-codec-glue.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CTRL_DIN_EN			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CTRL_CLK_INV			BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CTRL_LRCLK_INV			BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CTRL_I2S_IN_BCLK_SRC		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CTRL_DIN_LRCLK_SRC_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CTRL_DIN_LRCLK_SRC		(0x3 << CTRL_DIN_LRCLK_SRC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CTRL_BCLK_MCLK_SRC		GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CTRL_DIN_SKEW			GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CTRL_I2S_OUT_LANE_SRC		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AIU_ACODEC_OUT_CHMAX		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static const char * const aiu_acodec_ctrl_mux_texts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	"DISABLED", "I2S", "PCM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static int aiu_acodec_ctrl_mux_put_enum(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 					struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct snd_soc_component *component =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		snd_soc_dapm_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct snd_soc_dapm_context *dapm =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		snd_soc_dapm_kcontrol_dapm(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned int mux, changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	mux = snd_soc_enum_item_to_val(e, ucontrol->value.enumerated.item[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	changed = snd_soc_component_test_bits(component, e->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 					      CTRL_DIN_LRCLK_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 					      FIELD_PREP(CTRL_DIN_LRCLK_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 							 mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if (!changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* Force disconnect of the mux while updating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	snd_soc_dapm_mux_update_power(dapm, kcontrol, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	snd_soc_component_update_bits(component, e->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				      CTRL_DIN_LRCLK_SRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 				      CTRL_BCLK_MCLK_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				      FIELD_PREP(CTRL_DIN_LRCLK_SRC, mux) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 				      FIELD_PREP(CTRL_BCLK_MCLK_SRC, mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	snd_soc_dapm_mux_update_power(dapm, kcontrol, mux, e, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static SOC_ENUM_SINGLE_DECL(aiu_acodec_ctrl_mux_enum, AIU_ACODEC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			    CTRL_DIN_LRCLK_SRC_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			    aiu_acodec_ctrl_mux_texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static const struct snd_kcontrol_new aiu_acodec_ctrl_mux =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	SOC_DAPM_ENUM_EXT("ACodec Source", aiu_acodec_ctrl_mux_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			  snd_soc_dapm_get_enum_double,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			  aiu_acodec_ctrl_mux_put_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static const struct snd_kcontrol_new aiu_acodec_ctrl_out_enable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", AIU_ACODEC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				    CTRL_DIN_EN, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static const struct snd_soc_dapm_widget aiu_acodec_ctrl_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	SND_SOC_DAPM_MUX("ACODEC SRC", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			 &aiu_acodec_ctrl_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	SND_SOC_DAPM_SWITCH("ACODEC OUT EN", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			    &aiu_acodec_ctrl_out_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int aiu_acodec_ctrl_input_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 					   struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 					   struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct meson_codec_glue_input *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ret = meson_codec_glue_input_hw_params(substream, params, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* The glue will provide 1 lane out of the 4 to the output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	data = meson_codec_glue_input_get_data(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	data->params.channels_min = min_t(unsigned int, AIU_ACODEC_OUT_CHMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 					  data->params.channels_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	data->params.channels_max = min_t(unsigned int, AIU_ACODEC_OUT_CHMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 					  data->params.channels_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct snd_soc_dai_ops aiu_acodec_ctrl_input_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.hw_params	= aiu_acodec_ctrl_input_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.set_fmt	= meson_codec_glue_input_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct snd_soc_dai_ops aiu_acodec_ctrl_output_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.startup	= meson_codec_glue_output_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AIU_ACODEC_CTRL_FORMATS					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AIU_ACODEC_STREAM(xname, xsuffix, xchmax)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.stream_name	= xname " " xsuffix,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.channels_min	= 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.channels_max	= (xchmax),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.rate_min       = 5512,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.rate_max	= 192000,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.formats	= AIU_ACODEC_CTRL_FORMATS,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AIU_ACODEC_INPUT(xname) {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.name = "ACODEC CTRL " xname,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.playback = AIU_ACODEC_STREAM(xname, "Playback", 8),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.ops = &aiu_acodec_ctrl_input_ops,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.probe = meson_codec_glue_input_dai_probe,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.remove = meson_codec_glue_input_dai_remove,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AIU_ACODEC_OUTPUT(xname) {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.name = "ACODEC CTRL " xname,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.capture = AIU_ACODEC_STREAM(xname, "Capture", AIU_ACODEC_OUT_CHMAX), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.ops = &aiu_acodec_ctrl_output_ops,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct snd_soc_dai_driver aiu_acodec_ctrl_dai_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	[CTRL_I2S] = AIU_ACODEC_INPUT("ACODEC I2S IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	[CTRL_PCM] = AIU_ACODEC_INPUT("ACODEC PCM IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	[CTRL_OUT] = AIU_ACODEC_OUTPUT("ACODEC OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct snd_soc_dapm_route aiu_acodec_ctrl_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{ "ACODEC SRC", "I2S", "ACODEC I2S IN Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{ "ACODEC SRC", "PCM", "ACODEC PCM IN Playback" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ "ACODEC OUT EN", "Switch", "ACODEC SRC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ "ACODEC OUT Capture", NULL, "ACODEC OUT EN" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct snd_kcontrol_new aiu_acodec_ctrl_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	SOC_SINGLE("ACODEC I2S Lane Select", AIU_ACODEC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		   CTRL_I2S_OUT_LANE_SRC, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int aiu_acodec_of_xlate_dai_name(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 					struct of_phandle_args *args,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 					const char **dai_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return aiu_of_xlate_dai_name(component, args, dai_name, AIU_ACODEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int aiu_acodec_ctrl_component_probe(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * NOTE: Din Skew setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * According to the documentation, the following update adds one delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 * to the din line. Without this, the output saturates. This happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 * regardless of the link format (i2s or left_j) so it is not clear what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * it actually does but it seems to be required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	snd_soc_component_update_bits(component, AIU_ACODEC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				      CTRL_DIN_SKEW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				      FIELD_PREP(CTRL_DIN_SKEW, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct snd_soc_component_driver aiu_acodec_ctrl_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.name			= "AIU Internal DAC Codec Control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.probe			= aiu_acodec_ctrl_component_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.controls		= aiu_acodec_ctrl_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.num_controls		= ARRAY_SIZE(aiu_acodec_ctrl_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.dapm_widgets		= aiu_acodec_ctrl_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.num_dapm_widgets	= ARRAY_SIZE(aiu_acodec_ctrl_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.dapm_routes		= aiu_acodec_ctrl_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.num_dapm_routes	= ARRAY_SIZE(aiu_acodec_ctrl_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.of_xlate_dai_name	= aiu_acodec_of_xlate_dai_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.endianness		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.non_legacy_dai_naming	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int aiu_acodec_ctrl_register_component(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return snd_soc_register_component(dev, &aiu_acodec_ctrl_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 					  aiu_acodec_ctrl_dai_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 					  ARRAY_SIZE(aiu_acodec_ctrl_dai_drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }