^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // MediaTek ALSA SoC Audio DAI TDM Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "mt8183-afe-clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "mt8183-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "mt8183-interconnection.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "mt8183-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct mtk_afe_tdm_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) int bck_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int bck_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) int tdm_out_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int bck_invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int lck_invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int mclk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int mclk_multiple; /* according to sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int mclk_apll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) TDM_OUT_I2S = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) TDM_OUT_TDM = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) TDM_BCK_NON_INV = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) TDM_BCK_INV = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) TDM_LCK_NON_INV = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) TDM_LCK_INV = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) TDM_WLEN_16_BIT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) TDM_WLEN_32_BIT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) TDM_CHANNEL_BCK_16 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) TDM_CHANNEL_BCK_24 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) TDM_CHANNEL_BCK_32 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) TDM_CHANNEL_NUM_2 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) TDM_CHANNEL_NUM_4 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) TDM_CHANNEL_NUM_8 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) TDM_CH_START_O30_O31 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) TDM_CH_START_O32_O33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) TDM_CH_START_O34_O35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) TDM_CH_START_O36_O37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) TDM_CH_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) HDMI_BIT_WIDTH_16_BIT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) HDMI_BIT_WIDTH_32_BIT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static unsigned int get_hdmi_wlen(snd_pcm_format_t format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return snd_pcm_format_physical_width(format) <= 16 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) HDMI_BIT_WIDTH_16_BIT : HDMI_BIT_WIDTH_32_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static unsigned int get_tdm_wlen(snd_pcm_format_t format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return snd_pcm_format_physical_width(format) <= 16 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) TDM_WLEN_16_BIT : TDM_WLEN_32_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static unsigned int get_tdm_channel_bck(snd_pcm_format_t format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return snd_pcm_format_physical_width(format) <= 16 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static unsigned int get_tdm_lrck_width(snd_pcm_format_t format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return snd_pcm_format_physical_width(format) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static unsigned int get_tdm_ch(unsigned int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) switch (ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return TDM_CHANNEL_NUM_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return TDM_CHANNEL_NUM_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return TDM_CHANNEL_NUM_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static unsigned int get_tdm_ch_fixup(unsigned int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (channels > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else if (channels > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned int get_tdm_ch_per_sdata(unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (mode == TDM_OUT_TDM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return get_tdm_ch_fixup(channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* interconnection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) HDMI_CONN_CH0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) HDMI_CONN_CH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) HDMI_CONN_CH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) HDMI_CONN_CH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) HDMI_CONN_CH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) HDMI_CONN_CH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) HDMI_CONN_CH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) HDMI_CONN_CH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const char *const hdmi_conn_mux_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "CH0", "CH1", "CH2", "CH3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "CH4", "CH5", "CH6", "CH7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int hdmi_conn_mux_map_value[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) HDMI_CONN_CH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) HDMI_CONN_CH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) HDMI_CONN_CH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) HDMI_CONN_CH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) HDMI_CONN_CH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) HDMI_CONN_CH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) HDMI_CONN_CH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) HDMI_CONN_CH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) HDMI_O_0_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) HDMI_O_0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) hdmi_conn_mux_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) hdmi_conn_mux_map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct snd_kcontrol_new hdmi_ch0_mux_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) HDMI_O_1_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) HDMI_O_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) hdmi_conn_mux_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) hdmi_conn_mux_map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct snd_kcontrol_new hdmi_ch1_mux_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) HDMI_O_2_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) HDMI_O_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) hdmi_conn_mux_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) hdmi_conn_mux_map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct snd_kcontrol_new hdmi_ch2_mux_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) HDMI_O_3_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) HDMI_O_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) hdmi_conn_mux_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) hdmi_conn_mux_map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct snd_kcontrol_new hdmi_ch3_mux_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) HDMI_O_4_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) HDMI_O_4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) hdmi_conn_mux_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) hdmi_conn_mux_map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct snd_kcontrol_new hdmi_ch4_mux_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) HDMI_O_5_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) HDMI_O_5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) hdmi_conn_mux_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) hdmi_conn_mux_map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct snd_kcontrol_new hdmi_ch5_mux_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) HDMI_O_6_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) HDMI_O_6_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) hdmi_conn_mux_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) hdmi_conn_mux_map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct snd_kcontrol_new hdmi_ch6_mux_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) HDMI_O_7_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) HDMI_O_7_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) hdmi_conn_mux_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) hdmi_conn_mux_map_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct snd_kcontrol_new hdmi_ch7_mux_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SUPPLY_SEQ_APLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SUPPLY_SEQ_TDM_MCK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) SUPPLY_SEQ_TDM_BCK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __func__, w->name, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case SND_SOC_DAPM_PRE_PMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mt8183_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case SND_SOC_DAPM_POST_PMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mt8183_mck_disable(afe, tdm_priv->bck_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __func__, w->name, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case SND_SOC_DAPM_PRE_PMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mt8183_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case SND_SOC_DAPM_POST_PMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tdm_priv->mclk_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mt8183_mck_disable(afe, tdm_priv->mclk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) &hdmi_ch0_mux_control),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) &hdmi_ch1_mux_control),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &hdmi_ch2_mux_control),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) &hdmi_ch3_mux_control),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) &hdmi_ch4_mux_control),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) &hdmi_ch5_mux_control),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) &hdmi_ch6_mux_control),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) &hdmi_ch7_mux_control),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SND_SOC_DAPM_CLOCK_SUPPLY("aud_tdm_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mtk_tdm_bck_en_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mtk_tdm_mck_en_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct snd_soc_dapm_widget *sink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct snd_soc_dapm_widget *w = sink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int cur_apll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* which apll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) cur_apll = mt8183_get_apll_by_name(afe, source->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {"HDMI_CH0_MUX", "CH0", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {"HDMI_CH0_MUX", "CH1", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {"HDMI_CH0_MUX", "CH2", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {"HDMI_CH0_MUX", "CH3", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {"HDMI_CH0_MUX", "CH4", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {"HDMI_CH0_MUX", "CH5", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {"HDMI_CH0_MUX", "CH6", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {"HDMI_CH0_MUX", "CH7", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {"HDMI_CH1_MUX", "CH0", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {"HDMI_CH1_MUX", "CH1", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {"HDMI_CH1_MUX", "CH2", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {"HDMI_CH1_MUX", "CH3", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {"HDMI_CH1_MUX", "CH4", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {"HDMI_CH1_MUX", "CH5", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {"HDMI_CH1_MUX", "CH6", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {"HDMI_CH1_MUX", "CH7", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {"HDMI_CH2_MUX", "CH0", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {"HDMI_CH2_MUX", "CH1", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {"HDMI_CH2_MUX", "CH2", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {"HDMI_CH2_MUX", "CH3", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {"HDMI_CH2_MUX", "CH4", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {"HDMI_CH2_MUX", "CH5", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {"HDMI_CH2_MUX", "CH6", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {"HDMI_CH2_MUX", "CH7", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {"HDMI_CH3_MUX", "CH0", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {"HDMI_CH3_MUX", "CH1", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {"HDMI_CH3_MUX", "CH2", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {"HDMI_CH3_MUX", "CH3", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {"HDMI_CH3_MUX", "CH4", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {"HDMI_CH3_MUX", "CH5", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {"HDMI_CH3_MUX", "CH6", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {"HDMI_CH3_MUX", "CH7", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {"HDMI_CH4_MUX", "CH0", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {"HDMI_CH4_MUX", "CH1", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {"HDMI_CH4_MUX", "CH2", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {"HDMI_CH4_MUX", "CH3", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {"HDMI_CH4_MUX", "CH4", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {"HDMI_CH4_MUX", "CH5", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {"HDMI_CH4_MUX", "CH6", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {"HDMI_CH4_MUX", "CH7", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {"HDMI_CH5_MUX", "CH0", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {"HDMI_CH5_MUX", "CH1", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {"HDMI_CH5_MUX", "CH2", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {"HDMI_CH5_MUX", "CH3", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {"HDMI_CH5_MUX", "CH4", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {"HDMI_CH5_MUX", "CH5", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {"HDMI_CH5_MUX", "CH6", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {"HDMI_CH5_MUX", "CH7", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {"HDMI_CH6_MUX", "CH0", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {"HDMI_CH6_MUX", "CH1", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {"HDMI_CH6_MUX", "CH2", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {"HDMI_CH6_MUX", "CH3", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {"HDMI_CH6_MUX", "CH4", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {"HDMI_CH6_MUX", "CH5", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {"HDMI_CH6_MUX", "CH6", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {"HDMI_CH6_MUX", "CH7", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {"HDMI_CH7_MUX", "CH0", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {"HDMI_CH7_MUX", "CH1", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {"HDMI_CH7_MUX", "CH2", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {"HDMI_CH7_MUX", "CH3", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {"HDMI_CH7_MUX", "CH4", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {"HDMI_CH7_MUX", "CH5", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {"HDMI_CH7_MUX", "CH6", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {"HDMI_CH7_MUX", "CH7", "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {"TDM", NULL, "HDMI_CH0_MUX"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {"TDM", NULL, "HDMI_CH1_MUX"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {"TDM", NULL, "HDMI_CH2_MUX"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {"TDM", NULL, "HDMI_CH3_MUX"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {"TDM", NULL, "HDMI_CH4_MUX"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {"TDM", NULL, "HDMI_CH5_MUX"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {"TDM", NULL, "HDMI_CH6_MUX"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {"TDM", NULL, "HDMI_CH7_MUX"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {"TDM", NULL, "aud_tdm_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {"TDM", NULL, "TDM_BCK"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {"TDM_BCK", NULL, "TDM_MCK"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* dai ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct mtk_afe_tdm_priv *tdm_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int apll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int apll_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) apll = mt8183_get_apll_by_rate(afe, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) apll_rate = mt8183_get_apll_rate(afe, apll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!freq || freq > apll_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_warn(afe->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "%s(), freq(%d Hz) invalid\n", __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (apll_rate % freq != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_warn(afe->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "%s(), APLL cannot generate %d Hz", __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) tdm_priv->mclk_rate = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) tdm_priv->mclk_apll = apll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int tdm_id = dai->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[tdm_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned int tdm_out_mode = tdm_priv->tdm_out_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unsigned int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned int out_channels_per_sdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) get_tdm_ch_per_sdata(tdm_out_mode, channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) snd_pcm_format_t format = params_format(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int tdm_con = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* calculate mclk_rate, if not set explicitly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!tdm_priv->mclk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) mtk_dai_tdm_cal_mclk(afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tdm_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tdm_priv->mclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* calculate bck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) tdm_priv->bck_rate = rate *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) out_channels_per_sdata *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) snd_pcm_format_physical_width(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (tdm_priv->bck_rate > tdm_priv->mclk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_warn(afe->dev, "%s(), bck_rate > mclk_rate rate", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_warn(afe->dev, "%s(), bck cannot generate", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_info(afe->dev, "%s(), id %d, rate %d, channels %d, format %d, mclk_rate %d, bck_rate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tdm_id, rate, channels, format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tdm_priv->mclk_rate, tdm_priv->bck_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_info(afe->dev, "%s(), out_channels_per_sdata = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) __func__, out_channels_per_sdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* set tdm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (tdm_priv->bck_invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) regmap_update_bits(afe->regmap, AUDIO_TOP_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) BCK_INVERSE_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 0x1 << BCK_INVERSE_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (tdm_priv->lck_invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) tdm_con |= 1 << LRCK_INVERSE_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (tdm_priv->tdm_out_mode == TDM_OUT_I2S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) tdm_con |= 1 << DELAY_DATA_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else if (tdm_priv->tdm_out_mode == TDM_OUT_TDM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tdm_con |= 0 << DELAY_DATA_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) tdm_con |= 0 << LRCK_TDM_WIDTH_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) tdm_con |= 1 << LEFT_ALIGN_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) tdm_con |= get_tdm_wlen(format) << WLEN_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) tdm_con |= get_tdm_ch(out_channels_per_sdata) << CHANNEL_NUM_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (out_channels_per_sdata == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) switch (channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) tdm_con = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) AFE_HDMI_OUT_CH_NUM_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) channels << AFE_HDMI_OUT_CH_NUM_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) get_hdmi_wlen(format) << AFE_HDMI_OUT_BIT_WIDTH_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int mtk_dai_tdm_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* enable Out control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) AFE_HDMI_OUT_ON_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 0x1 << AFE_HDMI_OUT_ON_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* enable tdm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) regmap_update_bits(afe->regmap, AFE_TDM_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) TDM_EN_MASK_SFT, 0x1 << TDM_EN_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* disable tdm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) regmap_update_bits(afe->regmap, AFE_TDM_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) TDM_EN_MASK_SFT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* disable Out control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) AFE_HDMI_OUT_ON_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int clk_id, unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!tdm_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (dir != SND_SOC_CLOCK_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_info(afe->dev, "%s(), freq %d\n", __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int mtk_dai_tdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!tdm_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* DAI mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case SND_SOC_DAIFMT_I2S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) tdm_priv->tdm_out_mode = TDM_OUT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case SND_SOC_DAIFMT_DSP_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) tdm_priv->tdm_out_mode = TDM_OUT_TDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) tdm_priv->tdm_out_mode = TDM_OUT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* DAI clock inversion*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case SND_SOC_DAIFMT_NB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) tdm_priv->bck_invert = TDM_BCK_NON_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) tdm_priv->lck_invert = TDM_LCK_NON_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case SND_SOC_DAIFMT_NB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) tdm_priv->bck_invert = TDM_BCK_NON_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) tdm_priv->lck_invert = TDM_LCK_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case SND_SOC_DAIFMT_IB_NF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) tdm_priv->bck_invert = TDM_BCK_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) tdm_priv->lck_invert = TDM_LCK_NON_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case SND_SOC_DAIFMT_IB_IF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) tdm_priv->bck_invert = TDM_BCK_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) tdm_priv->lck_invert = TDM_LCK_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const struct snd_soc_dai_ops mtk_dai_tdm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .hw_params = mtk_dai_tdm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .trigger = mtk_dai_tdm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .set_sysclk = mtk_dai_tdm_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .set_fmt = mtk_dai_tdm_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* dai driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) SNDRV_PCM_RATE_88200 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SNDRV_PCM_RATE_96000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) SNDRV_PCM_RATE_176400 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) SNDRV_PCM_FMTBIT_S24_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .name = "TDM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .id = MT8183_DAI_TDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .stream_name = "TDM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .rates = MTK_TDM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .formats = MTK_TDM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .ops = &mtk_dai_tdm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int mt8183_dai_tdm_register(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct mtk_afe_tdm_priv *tdm_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct mtk_base_afe_dai *dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) list_add(&dai->list, &afe->sub_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dai->dai_drivers = mtk_dai_tdm_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dai->dapm_widgets = mtk_dai_tdm_widgets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dai->dapm_routes = mtk_dai_tdm_routes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (!tdm_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) tdm_priv->mclk_multiple = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) tdm_priv->bck_id = MT8183_I2S4_BCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) tdm_priv->mclk_id = MT8183_I2S4_MCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) afe_priv->dai_priv[MT8183_DAI_TDM] = tdm_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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