^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // MediaTek ALSA SoC Audio DAI ADDA Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "mt8183-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "mt8183-interconnection.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "mt8183-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) AUDIO_SDM_LEVEL_MUTE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) AUDIO_SDM_LEVEL_NORMAL = 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* if you change level normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* you need to change formula of hp impedance and dc trim too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DELAY_DATA_MISO1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DELAY_DATA_MISO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MTK_AFE_ADDA_DL_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MTK_AFE_ADDA_DL_RATE_11K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MTK_AFE_ADDA_DL_RATE_12K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MTK_AFE_ADDA_DL_RATE_16K = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MTK_AFE_ADDA_DL_RATE_22K = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MTK_AFE_ADDA_DL_RATE_24K = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MTK_AFE_ADDA_DL_RATE_32K = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MTK_AFE_ADDA_DL_RATE_44K = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MTK_AFE_ADDA_DL_RATE_48K = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MTK_AFE_ADDA_DL_RATE_96K = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MTK_AFE_ADDA_DL_RATE_192K = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MTK_AFE_ADDA_UL_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MTK_AFE_ADDA_UL_RATE_16K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MTK_AFE_ADDA_UL_RATE_32K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MTK_AFE_ADDA_UL_RATE_48K = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MTK_AFE_ADDA_UL_RATE_96K = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MTK_AFE_ADDA_UL_RATE_192K = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return MTK_AFE_ADDA_DL_RATE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return MTK_AFE_ADDA_DL_RATE_11K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 12000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return MTK_AFE_ADDA_DL_RATE_12K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return MTK_AFE_ADDA_DL_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return MTK_AFE_ADDA_DL_RATE_22K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case 24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return MTK_AFE_ADDA_DL_RATE_24K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return MTK_AFE_ADDA_DL_RATE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return MTK_AFE_ADDA_DL_RATE_44K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return MTK_AFE_ADDA_DL_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return MTK_AFE_ADDA_DL_RATE_96K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return MTK_AFE_ADDA_DL_RATE_192K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return MTK_AFE_ADDA_DL_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return MTK_AFE_ADDA_UL_RATE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return MTK_AFE_ADDA_UL_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return MTK_AFE_ADDA_UL_RATE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return MTK_AFE_ADDA_UL_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return MTK_AFE_ADDA_UL_RATE_96K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return MTK_AFE_ADDA_UL_RATE_192K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return MTK_AFE_ADDA_UL_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* dai component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) I_PCM_1_CAP_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) I_PCM_2_CAP_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) I_PCM_1_CAP_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) I_PCM_2_CAP_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) I_PCM_1_CAP_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) I_PCM_2_CAP_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __func__, w->name, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case SND_SOC_DAPM_PRE_PMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* update setting to dmic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (afe_priv->mtkaif_dmic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* mtkaif_rxif_data_mode = 1, dmic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* dmic mode, 3.25M*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0x0, 0xf << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0x0, 0x1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 0x0, 0x3 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* turn on dmic, ch1, ch2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0x1 << 1, 0x1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0x3 << 21, 0x3 << 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case SND_SOC_DAPM_POST_PMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) usleep_range(125, 135);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* mtkaif dmic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const char * const mt8183_adda_off_on_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "Off", "On"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct soc_enum mt8183_adda_enum[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_adda_off_on_str),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mt8183_adda_off_on_str),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int mt8183_adda_dmic_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int mt8183_adda_dmic_set(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ucontrol->value.enumerated.item[0] >= e->items)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) afe_priv->mtkaif_dmic = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_dmic %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __func__, kcontrol->id.name, afe_priv->mtkaif_dmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct snd_kcontrol_new mtk_adda_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SOC_ENUM_EXT("MTKAIF_DMIC", mt8183_adda_enum[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mt8183_adda_dmic_get, mt8183_adda_dmic_set),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SUPPLY_SEQ_ADDA_AFE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SUPPLY_SEQ_ADDA_DL_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SUPPLY_SEQ_ADDA_UL_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* adda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mtk_adda_dl_ch1_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mtk_adda_dl_ch2_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) AFE_ADDA_DL_SRC2_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) AFE_ADDA_UL_SRC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) UL_SRC_ON_TMP_CTL_SFT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mtk_adda_ul_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {"ADDA Playback", NULL, "ADDA_DL_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {"ADDA Playback", NULL, "ADDA_DL_CH2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* adda enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {"ADDA Playback", NULL, "ADDA Enable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {"ADDA Playback", NULL, "ADDA Playback Enable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {"ADDA Capture", NULL, "ADDA Enable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {"ADDA Capture", NULL, "ADDA Capture Enable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {"ADDA Playback", NULL, "mtkaif_26m_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {"ADDA Playback", NULL, "aud_dac_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {"ADDA Playback", NULL, "aud_dac_predis_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {"ADDA Capture", NULL, "mtkaif_26m_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {"ADDA Capture", NULL, "aud_adc_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int set_mtkaif_rx(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int delay_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int delay_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) switch (afe_priv->mtkaif_protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case MT8183_MTKAIF_PROTOCOL_2_CLK_P2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* mtkaif_rxif_clkinv_adc inverse for calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0x80010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (afe_priv->mtkaif_phase_cycle[0] >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) afe_priv->mtkaif_phase_cycle[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) delay_data = DELAY_DATA_MISO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) afe_priv->mtkaif_phase_cycle[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) delay_data = DELAY_DATA_MISO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) afe_priv->mtkaif_phase_cycle[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) AFE_ADDA_MTKAIF_RX_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) delay_data << MTKAIF_RXIF_DELAY_DATA_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) AFE_ADDA_MTKAIF_RX_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) delay_cycle << MTKAIF_RXIF_DELAY_CYCLE_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case MT8183_MTKAIF_PROTOCOL_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0x00010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case MT8183_MTKAIF_PROTOCOL_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* dai ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) __func__, dai->id, substream->stream, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int dl_src2_con0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int dl_src2_con1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* clean predistortion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* set sampling rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* set output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dl_src2_con0 |= 1 << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dl_src2_con0 |= 1 << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* turn off mute function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dl_src2_con0 |= (0x03 << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* set voice input data if input sample rate is 8k or 16k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (rate == 8000 || rate == 16000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dl_src2_con0 |= 0x01 << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* SA suggest apply -0.3db to audio/speech path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dl_src2_con1 = 0xf74f0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* turn on down-link gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* set sdm gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) AFE_ADDA_DL_SDM_DCCOMP_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ATTGAIN_CTL_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) AUDIO_SDM_LEVEL_NORMAL << ATTGAIN_CTL_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int voice_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int ul_src_con0 = 0; /* default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* set mtkaif protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) set_mtkaif_rx(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Using Internal ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) AFE_ADDA_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x0 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) voice_mode = adda_ul_rate_transform(afe, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* enable iir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) UL_IIR_ON_TMP_CTL_MASK_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* 35Hz @ 48k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_02_01, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) regmap_write(afe->regmap, AFE_ADDA_UL_SRC_CON0, ul_src_con0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* mtkaif_rxif_data_mode = 0, amic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) AFE_ADDA_MTKAIF_RX_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 0x1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0x0 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .hw_params = mtk_dai_adda_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* dai driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) SNDRV_PCM_RATE_96000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SNDRV_PCM_RATE_16000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) SNDRV_PCM_RATE_32000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SNDRV_PCM_RATE_48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) SNDRV_PCM_FMTBIT_S24_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "ADDA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .id = MT8183_DAI_ADDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .stream_name = "ADDA Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .rates = MTK_ADDA_PLAYBACK_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .formats = MTK_ADDA_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .stream_name = "ADDA Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .rates = MTK_ADDA_CAPTURE_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .formats = MTK_ADDA_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .ops = &mtk_dai_adda_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int mt8183_dai_adda_register(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct mtk_base_afe_dai *dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) list_add(&dai->list, &afe->sub_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dai->dai_drivers = mtk_dai_adda_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dai->controls = mtk_adda_controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dai->dapm_widgets = mtk_dai_adda_widgets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dai->dapm_routes = mtk_dai_adda_routes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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