^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Mediatek ALSA SoC AFE platform driver for 8183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "mt8183-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "mt8183-afe-clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "mt8183-interconnection.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "mt8183-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../common/mtk-afe-platform-driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../common/mtk-afe-fe-dai.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MTK_AFE_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MTK_AFE_RATE_11K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MTK_AFE_RATE_12K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MTK_AFE_RATE_384K = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MTK_AFE_RATE_16K = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MTK_AFE_RATE_22K = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MTK_AFE_RATE_24K = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MTK_AFE_RATE_130K = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MTK_AFE_RATE_32K = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MTK_AFE_RATE_44K = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MTK_AFE_RATE_48K = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MTK_AFE_RATE_88K = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MTK_AFE_RATE_96K = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MTK_AFE_RATE_176K = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MTK_AFE_RATE_192K = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MTK_AFE_RATE_260K = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MTK_AFE_DAI_MEMIF_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MTK_AFE_DAI_MEMIF_RATE_16K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MTK_AFE_DAI_MEMIF_RATE_32K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MTK_AFE_DAI_MEMIF_RATE_48K = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MTK_AFE_PCM_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MTK_AFE_PCM_RATE_16K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MTK_AFE_PCM_RATE_32K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MTK_AFE_PCM_RATE_48K = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int mt8183_general_rate_transform(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return MTK_AFE_RATE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return MTK_AFE_RATE_11K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case 12000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return MTK_AFE_RATE_12K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return MTK_AFE_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return MTK_AFE_RATE_22K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case 24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return MTK_AFE_RATE_24K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return MTK_AFE_RATE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return MTK_AFE_RATE_44K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return MTK_AFE_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return MTK_AFE_RATE_88K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return MTK_AFE_RATE_96K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case 130000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return MTK_AFE_RATE_130K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return MTK_AFE_RATE_176K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return MTK_AFE_RATE_192K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 260000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return MTK_AFE_RATE_260K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __func__, rate, MTK_AFE_RATE_48K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return MTK_AFE_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static unsigned int dai_memif_rate_transform(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return MTK_AFE_DAI_MEMIF_RATE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return MTK_AFE_DAI_MEMIF_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return MTK_AFE_DAI_MEMIF_RATE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return MTK_AFE_DAI_MEMIF_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return MTK_AFE_DAI_MEMIF_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int mt8183_rate_transform(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int rate, int aud_blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) switch (aud_blk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case MT8183_MEMIF_MOD_DAI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return dai_memif_rate_transform(dev, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return mt8183_general_rate_transform(dev, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct snd_pcm_hardware mt8183_afe_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SNDRV_PCM_INFO_MMAP_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .period_bytes_min = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .period_bytes_max = 4 * 48 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .periods_max = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .buffer_bytes_max = 8 * 48 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int mt8183_memif_fs(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct snd_soc_component *component =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int id = asoc_rtd_to_cpu(rtd, 0)->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return mt8183_rate_transform(afe->dev, rate, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct snd_soc_component *component =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return mt8183_general_rate_transform(afe->dev, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SNDRV_PCM_RATE_88200 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SNDRV_PCM_RATE_96000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SNDRV_PCM_RATE_176400 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SNDRV_PCM_RATE_16000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SNDRV_PCM_RATE_32000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SNDRV_PCM_RATE_48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SNDRV_PCM_FMTBIT_S24_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* FE DAIs: memory intefaces to CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .id = MT8183_MEMIF_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .stream_name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "DL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .id = MT8183_MEMIF_DL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .stream_name = "DL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .name = "DL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .id = MT8183_MEMIF_DL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .stream_name = "DL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .name = "UL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .id = MT8183_MEMIF_VUL12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .stream_name = "UL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .name = "UL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .id = MT8183_MEMIF_AWB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .stream_name = "UL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "UL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .id = MT8183_MEMIF_VUL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .stream_name = "UL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "UL4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .id = MT8183_MEMIF_AWB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .stream_name = "UL4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .name = "UL_MONO_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .id = MT8183_MEMIF_MOD_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .stream_name = "UL_MONO_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .rates = MTK_PCM_DAI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .id = MT8183_MEMIF_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .stream_name = "HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* dma widget & routes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) I_I2S0_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) I_I2S0_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) I_DL1_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) I_DL2_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) I_DL3_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) I_I2S2_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) I_DL1_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) I_DL2_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) I_DL3_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) I_I2S2_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) I_I2S2_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) I_I2S2_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* memif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) memif_ul_mono_1_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ARRAY_SIZE(memif_ul_mono_1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct snd_soc_dapm_route mt8183_memif_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {"UL1", NULL, "UL1_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {"UL1", NULL, "UL1_CH2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {"UL1_CH1", "I2S0_CH1", "I2S0"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {"UL1_CH2", "I2S0_CH2", "I2S0"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {"UL2", NULL, "UL2_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {"UL2", NULL, "UL2_CH2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {"UL2_CH1", "I2S2_CH1", "I2S2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {"UL2_CH2", "I2S2_CH2", "I2S2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {"UL3", NULL, "UL3_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {"UL3", NULL, "UL3_CH2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {"UL3_CH1", "I2S2_CH1", "I2S2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {"UL3_CH2", "I2S2_CH2", "I2S2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {"UL4", NULL, "UL4_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {"UL4", NULL, "UL4_CH2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = "mt8183-afe-pcm-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [MT8183_MEMIF_DL1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .id = MT8183_MEMIF_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .reg_ofs_base = AFE_DL1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .reg_ofs_cur = AFE_DL1_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .fs_shift = DL1_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .fs_maskbit = DL1_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .mono_shift = DL1_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .enable_shift = DL1_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .hd_align_reg = AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .hd_shift = DL1_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .hd_align_mshift = DL1_HD_ALIGN_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .agent_disable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .msb_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) [MT8183_MEMIF_DL2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .name = "DL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .id = MT8183_MEMIF_DL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .reg_ofs_base = AFE_DL2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .reg_ofs_cur = AFE_DL2_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .fs_shift = DL2_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .fs_maskbit = DL2_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .mono_shift = DL2_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .enable_shift = DL2_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .hd_align_reg = AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .hd_shift = DL2_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .hd_align_mshift = DL2_HD_ALIGN_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .agent_disable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .msb_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [MT8183_MEMIF_DL3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .name = "DL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .id = MT8183_MEMIF_DL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .reg_ofs_base = AFE_DL3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .reg_ofs_cur = AFE_DL3_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .fs_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .fs_shift = DL3_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .fs_maskbit = DL3_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .mono_shift = DL3_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .enable_shift = DL3_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .hd_align_reg = AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .hd_shift = DL3_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .hd_align_mshift = DL3_HD_ALIGN_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .agent_disable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .msb_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [MT8183_MEMIF_VUL2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = "VUL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .id = MT8183_MEMIF_VUL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .reg_ofs_base = AFE_VUL2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .reg_ofs_cur = AFE_VUL2_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .fs_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .fs_shift = VUL2_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .fs_maskbit = VUL2_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .mono_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .mono_shift = VUL2_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .enable_shift = VUL2_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .hd_align_reg = AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .hd_shift = VUL2_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .hd_align_mshift = VUL2_HD_ALIGN_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .agent_disable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .msb_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) [MT8183_MEMIF_AWB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .name = "AWB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .id = MT8183_MEMIF_AWB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .reg_ofs_base = AFE_AWB_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .reg_ofs_cur = AFE_AWB_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .fs_shift = AWB_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .fs_maskbit = AWB_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mono_shift = AWB_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .enable_shift = AWB_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .hd_align_reg = AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .hd_shift = AWB_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .hd_align_mshift = AWB_HD_ALIGN_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .agent_disable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .msb_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [MT8183_MEMIF_AWB2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .name = "AWB2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .id = MT8183_MEMIF_AWB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .reg_ofs_base = AFE_AWB2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .reg_ofs_cur = AFE_AWB2_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .fs_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .fs_shift = AWB2_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .fs_maskbit = AWB2_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .mono_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .mono_shift = AWB2_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .enable_shift = AWB2_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .hd_align_reg = AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .hd_shift = AWB2_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .hd_align_mshift = AWB2_ALIGN_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .agent_disable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .msb_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) [MT8183_MEMIF_VUL12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .name = "VUL12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .id = MT8183_MEMIF_VUL12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .reg_ofs_base = AFE_VUL_D2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .reg_ofs_cur = AFE_VUL_D2_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .fs_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .fs_shift = VUL12_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .fs_maskbit = VUL12_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .mono_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .mono_shift = VUL12_MONO_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .enable_shift = VUL12_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .hd_align_reg = AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .hd_shift = VUL12_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .hd_align_mshift = VUL12_HD_ALIGN_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .agent_disable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .msb_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) [MT8183_MEMIF_MOD_DAI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .name = "MOD_DAI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .id = MT8183_MEMIF_MOD_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .reg_ofs_base = AFE_MOD_DAI_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .reg_ofs_cur = AFE_MOD_DAI_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .fs_shift = MOD_DAI_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .fs_maskbit = MOD_DAI_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .mono_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .mono_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .enable_shift = MOD_DAI_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .hd_align_reg = AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .hd_shift = MOD_DAI_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .agent_disable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .msb_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) [MT8183_MEMIF_HDMI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .name = "HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .id = MT8183_MEMIF_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .reg_ofs_base = AFE_HDMI_OUT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .reg_ofs_cur = AFE_HDMI_OUT_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .fs_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .fs_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .fs_maskbit = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .mono_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .mono_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .enable_reg = -1, /* control in tdm for sync start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .enable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .hd_align_reg = AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .hd_shift = HDMI_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .hd_align_mshift = HDMI_HD_ALIGN_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .agent_disable_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .msb_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) [MT8183_IRQ_0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .id = MT8183_IRQ_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .irq_cnt_reg = AFE_IRQ_MCU_CNT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .irq_fs_reg = AFE_IRQ_MCU_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .irq_fs_shift = IRQ0_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .irq_en_shift = IRQ0_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .irq_clr_shift = IRQ0_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [MT8183_IRQ_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .id = MT8183_IRQ_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .irq_fs_reg = AFE_IRQ_MCU_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .irq_fs_shift = IRQ1_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .irq_en_shift = IRQ1_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .irq_clr_shift = IRQ1_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) [MT8183_IRQ_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .id = MT8183_IRQ_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .irq_fs_reg = AFE_IRQ_MCU_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .irq_fs_shift = IRQ2_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .irq_en_shift = IRQ2_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .irq_clr_shift = IRQ2_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [MT8183_IRQ_3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .id = MT8183_IRQ_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .irq_fs_reg = AFE_IRQ_MCU_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .irq_fs_shift = IRQ3_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .irq_en_shift = IRQ3_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .irq_clr_shift = IRQ3_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) [MT8183_IRQ_4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .id = MT8183_IRQ_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .irq_fs_reg = AFE_IRQ_MCU_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .irq_fs_shift = IRQ4_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .irq_en_shift = IRQ4_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .irq_clr_shift = IRQ4_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) [MT8183_IRQ_5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .id = MT8183_IRQ_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .irq_cnt_reg = AFE_IRQ_MCU_CNT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .irq_fs_reg = AFE_IRQ_MCU_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .irq_fs_shift = IRQ5_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .irq_en_shift = IRQ5_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .irq_clr_shift = IRQ5_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [MT8183_IRQ_6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .id = MT8183_IRQ_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .irq_cnt_reg = AFE_IRQ_MCU_CNT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .irq_fs_reg = AFE_IRQ_MCU_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .irq_fs_shift = IRQ6_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .irq_en_shift = IRQ6_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .irq_clr_shift = IRQ6_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [MT8183_IRQ_7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .id = MT8183_IRQ_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .irq_fs_reg = AFE_IRQ_MCU_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .irq_fs_shift = IRQ7_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .irq_en_shift = IRQ7_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .irq_clr_shift = IRQ7_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [MT8183_IRQ_8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .id = MT8183_IRQ_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .irq_cnt_reg = AFE_IRQ_MCU_CNT8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .irq_fs_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .irq_fs_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .irq_fs_maskbit = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .irq_en_shift = IRQ8_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .irq_clr_shift = IRQ8_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [MT8183_IRQ_11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .id = MT8183_IRQ_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .irq_cnt_reg = AFE_IRQ_MCU_CNT11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .irq_fs_reg = AFE_IRQ_MCU_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .irq_fs_shift = IRQ11_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .irq_en_shift = IRQ11_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .irq_clr_shift = IRQ11_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [MT8183_IRQ_12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .id = MT8183_IRQ_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .irq_cnt_reg = AFE_IRQ_MCU_CNT12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .irq_fs_reg = AFE_IRQ_MCU_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .irq_fs_shift = IRQ12_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .irq_en_reg = AFE_IRQ_MCU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .irq_en_shift = IRQ12_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .irq_clr_shift = IRQ12_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* these auto-gen reg has read-only bit, so put it as volatile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* volatile reg cannot be cached, so cannot be set when power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case AUDIO_TOP_CON0: /* reg bit controlled by CCF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) case AUDIO_TOP_CON1: /* reg bit controlled by CCF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case AUDIO_TOP_CON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case AFE_DL1_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) case AFE_DL1_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case AFE_DL2_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) case AFE_DL2_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) case AFE_AWB_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case AFE_AWB_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case AFE_VUL_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case AFE_VUL_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case AFE_MEMIF_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) case AFE_MEMIF_MON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case AFE_MEMIF_MON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case AFE_MEMIF_MON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case AFE_MEMIF_MON4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) case AFE_MEMIF_MON5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case AFE_MEMIF_MON6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case AFE_MEMIF_MON7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case AFE_MEMIF_MON8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case AFE_MEMIF_MON9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case AFE_ADDA_SRC_DEBUG_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case AFE_ADDA_SRC_DEBUG_MON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case AFE_ADDA_UL_SRC_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case AFE_ADDA_UL_SRC_MON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case AFE_SIDETONE_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case AFE_SIDETONE_CON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case AFE_SIDETONE_COEFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case AFE_BUS_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case AFE_MRGIF_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case AFE_MRGIF_MON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case AFE_MRGIF_MON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) case AFE_I2S_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case AFE_DAC_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case AFE_VUL2_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case AFE_VUL2_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case AFE_IRQ0_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case AFE_IRQ6_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case AFE_MOD_DAI_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case AFE_MOD_DAI_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case AFE_VUL_D2_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case AFE_VUL_D2_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case AFE_DL3_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case AFE_DL3_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case AFE_HDMI_OUT_CON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case AFE_HDMI_OUT_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case AFE_HDMI_OUT_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case AFE_IRQ3_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case AFE_IRQ4_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case AFE_IRQ_MCU_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case AFE_IRQ_MCU_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) case AFE_IRQ_MCU_MON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case AFE_IRQ1_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case AFE_IRQ2_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case AFE_IRQ1_MCU_EN_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case AFE_IRQ5_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case AFE_IRQ7_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case AFE_GAIN1_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) case AFE_GAIN2_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case AFE_SRAM_DELSEL_CON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case AFE_SRAM_DELSEL_CON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case AFE_SRAM_DELSEL_CON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case AFE_ASRC_2CH_CON12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case AFE_ASRC_2CH_CON13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case PCM_INTF_CON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case FPGA_CFG0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case FPGA_CFG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case FPGA_CFG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case FPGA_CFG3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case AUDIO_TOP_DBG_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case AUDIO_TOP_DBG_MON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case AFE_IRQ8_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case AFE_IRQ11_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case AFE_IRQ12_MCU_CNT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case AFE_CBIP_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case AFE_CBIP_SLV_MUX_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) case AFE_CBIP_SLV_DECODER_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case AFE_ADDA6_SRC_DEBUG_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case AFE_ADD6A_UL_SRC_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case AFE_ADDA6_UL_SRC_MON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case AFE_DL1_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case AFE_DL2_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case AFE_AWB_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case AFE_VUL_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) case AFE_VUL2_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case AFE_MOD_DAI_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case AFE_VUL_D2_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case AFE_DL3_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case AFE_HDMI_OUT_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) case AFE_AWB2_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case AFE_AWB2_CUR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case AFE_AWB2_CUR_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case AFE_ADDA_DL_SDM_FIFO_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case AFE_ADDA_DL_SRC_LCH_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) case AFE_ADDA_DL_SRC_RCH_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) case AFE_ADDA_DL_SDM_OUT_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) case AFE_CONNSYS_I2S_MON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case AFE_ASRC_2CH_CON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case AFE_ASRC_2CH_CON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) case AFE_ASRC_2CH_CON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case AFE_ASRC_2CH_CON4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case AFE_ASRC_2CH_CON5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case AFE_ASRC_2CH_CON7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case AFE_ASRC_2CH_CON8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case AFE_MEMIF_MON12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case AFE_MEMIF_MON13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case AFE_MEMIF_MON14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case AFE_MEMIF_MON15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case AFE_MEMIF_MON16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case AFE_MEMIF_MON17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case AFE_MEMIF_MON18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case AFE_MEMIF_MON19:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case AFE_MEMIF_MON20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case AFE_MEMIF_MON21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case AFE_MEMIF_MON22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case AFE_MEMIF_MON23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) case AFE_MEMIF_MON24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case AFE_ADDA_MTKAIF_MON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case AFE_ADDA_MTKAIF_MON1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) case AFE_AUD_PAD_TOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case AFE_GENERAL1_ASRC_2CH_CON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) case AFE_GENERAL1_ASRC_2CH_CON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case AFE_GENERAL1_ASRC_2CH_CON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case AFE_GENERAL1_ASRC_2CH_CON4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case AFE_GENERAL1_ASRC_2CH_CON5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case AFE_GENERAL1_ASRC_2CH_CON7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case AFE_GENERAL1_ASRC_2CH_CON8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) case AFE_GENERAL1_ASRC_2CH_CON12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case AFE_GENERAL1_ASRC_2CH_CON13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case AFE_GENERAL2_ASRC_2CH_CON0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case AFE_GENERAL2_ASRC_2CH_CON2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case AFE_GENERAL2_ASRC_2CH_CON3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case AFE_GENERAL2_ASRC_2CH_CON4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case AFE_GENERAL2_ASRC_2CH_CON5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case AFE_GENERAL2_ASRC_2CH_CON7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case AFE_GENERAL2_ASRC_2CH_CON8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case AFE_GENERAL2_ASRC_2CH_CON12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case AFE_GENERAL2_ASRC_2CH_CON13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const struct regmap_config mt8183_afe_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .volatile_reg = mt8183_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .max_register = AFE_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .num_reg_defaults_raw = AFE_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct mtk_base_afe *afe = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct mtk_base_afe_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned int status_mcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned int mcu_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) irqreturn_t irq_ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* get irq that is sent to MCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* only care IRQ which is sent to MCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (ret || status_mcu == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) __func__, ret, status, mcu_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) irq_ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) for (i = 0; i < MT8183_MEMIF_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct mtk_base_afe_memif *memif = &afe->memif[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (!memif->substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (memif->irq_usage < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) irq = &afe->irqs[memif->irq_usage];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (status_mcu & (1 << irq->irq_data->irq_en_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) snd_pcm_period_elapsed(memif->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* clear irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) regmap_write(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) status_mcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return irq_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int mt8183_afe_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct mtk_base_afe *afe = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) goto skip_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* disable AFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret = regmap_read_poll_timeout(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) AFE_DAC_MON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) (value & AFE_ON_RETM_MASK_SFT) == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) 1 * 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* make sure all irq status are cleared, twice intended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* cache only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) regcache_cache_only(afe->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) regcache_mark_dirty(afe->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) skip_regmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return mt8183_afe_disable_clock(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int mt8183_afe_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct mtk_base_afe *afe = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret = mt8183_afe_enable_clock(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) goto skip_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) regcache_cache_only(afe->regmap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) regcache_sync(afe->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* enable audio sys DCM for power saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* force cpu use 8_24 format when writing 32bit data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* set all output port to 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* enable AFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) skip_regmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int mt8183_afe_component_probe(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return mtk_afe_add_sub_dai_control(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static const struct snd_soc_component_driver mt8183_afe_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .name = AFE_PCM_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .probe = mt8183_afe_component_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .pointer = mtk_afe_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .pcm_construct = mtk_afe_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int mt8183_dai_memif_register(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct mtk_base_afe_dai *dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (!dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) list_add(&dai->list, &afe->sub_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dai->dai_drivers = mt8183_memif_dai_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dai->dapm_widgets = mt8183_memif_widgets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dai->dapm_routes = mt8183_memif_routes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) typedef int (*dai_register_cb)(struct mtk_base_afe *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static const dai_register_cb dai_register_cbs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) mt8183_dai_adda_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) mt8183_dai_i2s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) mt8183_dai_pcm_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) mt8183_dai_tdm_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) mt8183_dai_hostless_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) mt8183_dai_memif_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct mtk_base_afe *afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct mt8183_afe_private *afe_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) int i, irq_id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (!afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) platform_set_drvdata(pdev, afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (!afe->platform_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) afe->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev = afe->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* initial audio related clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ret = mt8183_init_clock(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dev_err(dev, "init clock error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* regmap init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (IS_ERR(afe->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dev_err(dev, "could not get regmap from parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret = PTR_ERR(afe->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) rstc = devm_reset_control_get(dev, "audiosys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (IS_ERR(rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ret = PTR_ERR(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev_err(dev, "could not get audiosys reset:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) ret = reset_control_reset(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dev_err(dev, "failed to trigger audio reset:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* enable clock for regcache get default value from hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) afe_priv->pm_runtime_bypass_reg_ctl = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) afe_priv->pm_runtime_bypass_reg_ctl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) regcache_cache_only(afe->regmap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) regcache_mark_dirty(afe->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* init memif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) afe->memif_size = MT8183_MEMIF_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (!afe->memif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) for (i = 0; i < afe->memif_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) afe->memif[i].data = &memif_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) afe->memif[i].irq_usage = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) afe->memif[MT8183_MEMIF_HDMI].const_irq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) mutex_init(&afe->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* init memif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* irq initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) afe->irqs_size = MT8183_IRQ_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (!afe->irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) for (i = 0; i < afe->irqs_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) afe->irqs[i].irq_data = &irq_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* request irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) irq_id = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (irq_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ret = irq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) dev_err(dev, "could not request_irq for asys-isr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* init sub_dais */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) INIT_LIST_HEAD(&afe->sub_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret = dai_register_cbs[i](afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* init dai_driver and component_driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = mtk_afe_combine_sub_dai(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) afe->mtk_afe_hardware = &mt8183_afe_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) afe->memif_fs = mt8183_memif_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) afe->irq_fs = mt8183_irq_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) afe->runtime_resume = mt8183_afe_runtime_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) afe->runtime_suspend = mt8183_afe_runtime_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* register component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) &mt8183_afe_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dev_warn(dev, "err_platform\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ret = devm_snd_soc_register_component(afe->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) &mt8183_afe_pcm_dai_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) afe->dai_drivers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) afe->num_dai_drivers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dev_warn(dev, "err_dai_component\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static int mt8183_afe_pcm_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) mt8183_afe_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static const struct of_device_id mt8183_afe_pcm_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) { .compatible = "mediatek,mt8183-audio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static const struct dev_pm_ops mt8183_afe_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) SET_RUNTIME_PM_OPS(mt8183_afe_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) mt8183_afe_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static struct platform_driver mt8183_afe_pcm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .name = "mt8183-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .of_match_table = mt8183_afe_pcm_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .pm = &mt8183_afe_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .probe = mt8183_afe_pcm_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .remove = mt8183_afe_pcm_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) module_platform_driver(mt8183_afe_pcm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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