Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * mt8183-afe-clk.h  --  Mediatek 8183 afe clock ctrl definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _MT8183_AFE_CLK_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _MT8183_AFE_CLK_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* APLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define APLL1_W_NAME "APLL1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define APLL2_W_NAME "APLL2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	MT8183_APLL1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	MT8183_APLL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct mtk_base_afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int mt8183_init_clock(struct mtk_base_afe *afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int mt8183_afe_enable_clock(struct mtk_base_afe *afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int mt8183_afe_disable_clock(struct mtk_base_afe *afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int mt8183_apll1_enable(struct mtk_base_afe *afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void mt8183_apll1_disable(struct mtk_base_afe *afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int mt8183_apll2_enable(struct mtk_base_afe *afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void mt8183_apll2_disable(struct mtk_base_afe *afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif