^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // mt8183-afe-clk.c -- Mediatek 8183 afe clock ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "mt8183-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "mt8183-afe-clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "mt8183-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) CLK_AFE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) CLK_TML,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) CLK_APLL22M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) CLK_APLL24M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) CLK_APLL1_TUNER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) CLK_APLL2_TUNER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) CLK_I2S1_BCLK_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) CLK_I2S2_BCLK_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) CLK_I2S3_BCLK_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) CLK_I2S4_BCLK_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) CLK_INFRA_SYS_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) CLK_MUX_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) CLK_MUX_AUDIOINTBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) CLK_TOP_SYSPLL_D2_D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* apll related mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CLK_TOP_MUX_AUD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) CLK_TOP_APLL1_CK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CLK_TOP_MUX_AUD_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CLK_TOP_APLL2_CK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CLK_TOP_MUX_AUD_ENG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CLK_TOP_APLL1_D8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CLK_TOP_MUX_AUD_ENG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) CLK_TOP_APLL2_D8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CLK_TOP_I2S0_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CLK_TOP_I2S1_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CLK_TOP_I2S2_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CLK_TOP_I2S3_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CLK_TOP_I2S4_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CLK_TOP_I2S5_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CLK_TOP_APLL12_DIV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CLK_TOP_APLL12_DIV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CLK_TOP_APLL12_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CLK_TOP_APLL12_DIV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CLK_TOP_APLL12_DIV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) CLK_TOP_APLL12_DIVB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) CLK_CLK26M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) CLK_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const char *aud_clks[CLK_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [CLK_AFE] = "aud_afe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [CLK_TML] = "aud_tml_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [CLK_APLL22M] = "aud_apll22m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [CLK_APLL24M] = "aud_apll24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [CLK_APLL1_TUNER] = "aud_apll1_tuner_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [CLK_I2S1_BCLK_SW] = "aud_i2s1_bclk_sw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [CLK_I2S2_BCLK_SW] = "aud_i2s2_bclk_sw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [CLK_I2S3_BCLK_SW] = "aud_i2s3_bclk_sw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [CLK_I2S4_BCLK_SW] = "aud_i2s4_bclk_sw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [CLK_MUX_AUDIO] = "top_mux_audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [CLK_MUX_AUDIOINTBUS] = "top_mux_aud_intbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [CLK_TOP_SYSPLL_D2_D4] = "top_syspll_d2_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [CLK_TOP_APLL1_CK] = "top_apll1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [CLK_TOP_APLL2_CK] = "top_apll2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [CLK_TOP_APLL1_D8] = "top_apll1_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [CLK_TOP_APLL2_D8] = "top_apll2_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [CLK_TOP_APLL12_DIV3] = "top_apll12_div3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [CLK_TOP_APLL12_DIVB] = "top_apll12_divb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [CLK_CLK26M] = "top_clk26m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int mt8183_init_clock(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!afe_priv->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) for (i = 0; i < CLK_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (IS_ERR(afe_priv->clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __func__, aud_clks[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PTR_ERR(afe_priv->clk[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return PTR_ERR(afe_priv->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int mt8183_afe_enable_clock(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto CLK_INFRA_SYS_AUDIO_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __func__, aud_clks[CLK_MUX_AUDIO], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto CLK_MUX_AUDIO_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __func__, aud_clks[CLK_MUX_AUDIO],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) aud_clks[CLK_CLK26M], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) goto CLK_MUX_AUDIO_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto CLK_MUX_AUDIO_INTBUS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) afe_priv->clk[CLK_TOP_SYSPLL_D2_D4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __func__, aud_clks[CLK_MUX_AUDIOINTBUS],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) aud_clks[CLK_TOP_SYSPLL_D2_D4], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto CLK_MUX_AUDIO_INTBUS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __func__, aud_clks[CLK_AFE], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto CLK_AFE_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __func__, aud_clks[CLK_I2S1_BCLK_SW], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) goto CLK_I2S1_BCLK_SW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __func__, aud_clks[CLK_I2S2_BCLK_SW], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) goto CLK_I2S2_BCLK_SW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __func__, aud_clks[CLK_I2S3_BCLK_SW], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto CLK_I2S3_BCLK_SW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __func__, aud_clks[CLK_I2S4_BCLK_SW], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto CLK_I2S4_BCLK_SW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CLK_I2S4_BCLK_SW_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CLK_I2S3_BCLK_SW_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CLK_I2S2_BCLK_SW_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CLK_I2S1_BCLK_SW_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CLK_AFE_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CLK_MUX_AUDIO_INTBUS_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CLK_MUX_AUDIO_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CLK_INFRA_SYS_AUDIO_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int mt8183_afe_disable_clock(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_disable_unprepare(afe_priv->clk[CLK_I2S4_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* apll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) goto ERR_ENABLE_CLK_TOP_MUX_AUD_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) afe_priv->clk[CLK_TOP_APLL1_CK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __func__, aud_clks[CLK_TOP_MUX_AUD_1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) aud_clks[CLK_TOP_APLL1_CK], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto ERR_SELECT_CLK_TOP_MUX_AUD_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* 180.6336 / 8 = 22.5792MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) afe_priv->clk[CLK_TOP_APLL1_D8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) aud_clks[CLK_TOP_APLL1_D8], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) aud_clks[CLK_CLK26M], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto EXIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __func__, aud_clks[CLK_TOP_MUX_AUD_1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) aud_clks[CLK_CLK26M], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) goto EXIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ERR_SELECT_CLK_TOP_MUX_AUD_ENG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ERR_SELECT_CLK_TOP_MUX_AUD_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ERR_ENABLE_CLK_TOP_MUX_AUD_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto ERR_ENABLE_CLK_TOP_MUX_AUD_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) afe_priv->clk[CLK_TOP_APLL2_CK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __func__, aud_clks[CLK_TOP_MUX_AUD_2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) aud_clks[CLK_TOP_APLL2_CK], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto ERR_SELECT_CLK_TOP_MUX_AUD_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* 196.608 / 8 = 24.576MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) afe_priv->clk[CLK_TOP_APLL2_D8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) aud_clks[CLK_TOP_APLL2_D8], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) aud_clks[CLK_CLK26M], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) goto EXIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __func__, aud_clks[CLK_TOP_MUX_AUD_2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) aud_clks[CLK_CLK26M], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto EXIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ERR_SELECT_CLK_TOP_MUX_AUD_ENG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ERR_SELECT_CLK_TOP_MUX_AUD_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ERR_ENABLE_CLK_TOP_MUX_AUD_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int mt8183_apll1_enable(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* setting for APLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) apll1_mux_setting(afe, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __func__, aud_clks[CLK_APLL22M], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto ERR_CLK_APLL22M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __func__, aud_clks[CLK_APLL1_TUNER], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto ERR_CLK_APLL1_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x0000FFF7, 0x00000832);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) AFE_22M_ON_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x1 << AFE_22M_ON_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ERR_CLK_APLL1_TUNER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ERR_CLK_APLL22M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) void mt8183_apll1_disable(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) AFE_22M_ON_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x0 << AFE_22M_ON_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) apll1_mux_setting(afe, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int mt8183_apll2_enable(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* setting for APLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) apll2_mux_setting(afe, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) __func__, aud_clks[CLK_APLL24M], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto ERR_CLK_APLL24M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) __func__, aud_clks[CLK_APLL2_TUNER], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) goto ERR_CLK_APLL2_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0x0000FFF7, 0x00000634);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) AFE_24M_ON_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0x1 << AFE_24M_ON_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ERR_CLK_APLL2_TUNER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ERR_CLK_APLL24M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) void mt8183_apll2_disable(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) AFE_24M_ON_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 0x0 << AFE_24M_ON_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) apll2_mux_setting(afe, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return (apll == MT8183_APLL1) ? 180633600 : 196608000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return ((rate % 8000) == 0) ? MT8183_APLL2 : MT8183_APLL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (strcmp(name, APLL1_W_NAME) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return MT8183_APLL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return MT8183_APLL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* mck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct mt8183_mck_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int m_sel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int div_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct mt8183_mck_div mck_div[MT8183_MCK_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) [MT8183_I2S0_MCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .m_sel_id = CLK_TOP_I2S0_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .div_clk_id = CLK_TOP_APLL12_DIV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [MT8183_I2S1_MCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .m_sel_id = CLK_TOP_I2S1_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .div_clk_id = CLK_TOP_APLL12_DIV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) [MT8183_I2S2_MCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .m_sel_id = CLK_TOP_I2S2_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .div_clk_id = CLK_TOP_APLL12_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [MT8183_I2S3_MCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .m_sel_id = CLK_TOP_I2S3_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .div_clk_id = CLK_TOP_APLL12_DIV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [MT8183_I2S4_MCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .m_sel_id = CLK_TOP_I2S4_M_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .div_clk_id = CLK_TOP_APLL12_DIV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [MT8183_I2S4_BCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .m_sel_id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .div_clk_id = CLK_TOP_APLL12_DIVB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [MT8183_I2S5_MCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .m_sel_id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .div_clk_id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int apll = mt8183_get_apll_by_rate(afe, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int apll_clk_id = apll == MT8183_APLL1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int m_sel_id = mck_div[mck_id].m_sel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int div_clk_id = mck_div[mck_id].div_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* i2s5 mck not support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (mck_id == MT8183_I2S5_MCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* select apll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (m_sel_id >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) __func__, aud_clks[m_sel_id], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) goto ERR_ENABLE_MCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = clk_set_parent(afe_priv->clk[m_sel_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) afe_priv->clk[apll_clk_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __func__, aud_clks[m_sel_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) aud_clks[apll_clk_id], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) goto ERR_SELECT_MCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* enable div, set rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) __func__, aud_clks[div_clk_id], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) goto ERR_ENABLE_MCLK_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) __func__, aud_clks[div_clk_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) rate, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) goto ERR_SET_MCLK_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ERR_SET_MCLK_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) clk_disable_unprepare(afe_priv->clk[div_clk_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ERR_ENABLE_MCLK_DIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ERR_SELECT_MCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (m_sel_id >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) clk_disable_unprepare(afe_priv->clk[m_sel_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ERR_ENABLE_MCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct mt8183_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int m_sel_id = mck_div[mck_id].m_sel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int div_clk_id = mck_div[mck_id].div_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* i2s5 mck not support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (mck_id == MT8183_I2S5_MCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) clk_disable_unprepare(afe_priv->clk[div_clk_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (m_sel_id >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) clk_disable_unprepare(afe_priv->clk[m_sel_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags