^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Mediatek 8173 ALSA SoC AFE platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Koro Chen <koro.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Sascha Hauer <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Hidalgo Huang <hidalgo.huang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Ir Lian <ir.lian@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "mt8173-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../common/mtk-base-afe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../common/mtk-afe-platform-driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "../common/mtk-afe-fe-dai.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * R E G I S T E R D E F I N I T I O N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AUDIO_TOP_CON0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AUDIO_TOP_CON1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AFE_DAC_CON0 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AFE_DAC_CON1 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AFE_I2S_CON1 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AFE_I2S_CON2 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AFE_CONN_24BIT 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AFE_MEMIF_MSB 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AFE_CONN1 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AFE_CONN2 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AFE_CONN3 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AFE_CONN7 0x0460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AFE_CONN8 0x0464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AFE_HDMI_CONN0 0x0390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Memory interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AFE_DL1_BASE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AFE_DL1_CUR 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AFE_DL1_END 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AFE_DL2_BASE 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AFE_DL2_CUR 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AFE_AWB_BASE 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AFE_AWB_CUR 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AFE_VUL_BASE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AFE_VUL_CUR 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AFE_VUL_END 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AFE_DAI_BASE 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AFE_DAI_CUR 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AFE_MOD_PCM_BASE 0x0330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AFE_MOD_PCM_CUR 0x033c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AFE_HDMI_OUT_BASE 0x0374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AFE_HDMI_OUT_CUR 0x0378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AFE_HDMI_OUT_END 0x037c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AFE_ADDA_TOP_CON0 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AFE_ADDA2_TOP_CON0 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AFE_HDMI_OUT_CON0 0x0370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AFE_IRQ_MCU_CON 0x03a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AFE_IRQ_STATUS 0x03a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AFE_IRQ_CLR 0x03a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AFE_IRQ_CNT1 0x03ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AFE_IRQ_CNT2 0x03b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AFE_IRQ_MCU_EN 0x03b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AFE_IRQ_CNT5 0x03bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AFE_IRQ_CNT7 0x03dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AFE_TDM_CON1 0x0548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AFE_TDM_CON2 0x054c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AFE_IRQ_STATUS_BITS 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* AUDIO_TOP_CON0 (0x0000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AUD_TCON0_PDN_SPDF (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AUD_TCON0_PDN_HDMI (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AUD_TCON0_PDN_24M (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AUD_TCON0_PDN_22M (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AUD_TCON0_PDN_AFE (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* AFE_I2S_CON1 (0x0034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AFE_I2S_CON1_EN (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* AFE_I2S_CON2 (0x0038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AFE_I2S_CON2_EN (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* AFE_CONN_24BIT (0x006c) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AFE_CONN_24BIT_O04 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AFE_CONN_24BIT_O03 (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* AFE_HDMI_CONN0 (0x0390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* AFE_TDM_CON1 (0x0548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AFE_TDM_CON1_LRCK_INV (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AFE_TDM_CON1_BCK_INV (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AFE_TDM_CON1_EN (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum afe_tdm_ch_start {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) AFE_TDM_CH_START_O30_O31 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) AFE_TDM_CH_START_O32_O33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) AFE_TDM_CH_START_O34_O35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) AFE_TDM_CH_START_O36_O37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) AFE_TDM_CH_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const unsigned int mt8173_afe_backup_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) AUDIO_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) AFE_CONN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) AFE_CONN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) AFE_CONN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) AFE_CONN8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) AFE_DL1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) AFE_DL1_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) AFE_VUL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) AFE_VUL_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) AFE_HDMI_OUT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) AFE_HDMI_OUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct mt8173_afe_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct clk *clocks[MT8173_CLK_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct snd_pcm_hardware mt8173_afe_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .buffer_bytes_max = 256 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .period_bytes_min = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .period_bytes_max = 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .periods_max = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct mt8173_afe_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int regvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .rate = 8000, .regvalue = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .rate = 11025, .regvalue = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .rate = 12000, .regvalue = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { .rate = 16000, .regvalue = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .rate = 22050, .regvalue = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .rate = 24000, .regvalue = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .rate = 32000, .regvalue = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .rate = 44100, .regvalue = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .rate = 48000, .regvalue = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .rate = 88000, .regvalue = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .rate = 96000, .regvalue = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .rate = 174000, .regvalue = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .rate = 192000, .regvalue = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int mt8173_afe_i2s_fs(unsigned int sample_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (mt8173_afe_i2s_rates[i].rate == sample_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return mt8173_afe_i2s_rates[i].regvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int fs = mt8173_afe_i2s_fs(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (fs < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* from external ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* set input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val = AFE_I2S_CON2_LOW_JITTER_CLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) AFE_I2S_CON2_RATE(fs) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) AFE_I2S_CON2_FORMAT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* set output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val = AFE_I2S_CON1_LOW_JITTER_CLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) AFE_I2S_CON1_RATE(fs) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) AFE_I2S_CON1_FORMAT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) regmap_read(afe->regmap, AFE_I2S_CON2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!!(val & AFE_I2S_CON2_EN) == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct clk *m_ck, struct clk *b_ck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (m_ck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = clk_prepare_enable(m_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(afe->dev, "Failed to enable m_ck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (b_ck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = clk_prepare_enable(b_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(afe->dev, "Failed to enable b_ck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct clk *m_ck, unsigned int mck_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct clk *b_ck, unsigned int bck_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (m_ck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = clk_set_rate(m_ck, mck_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(afe->dev, "Failed to set m_ck rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (b_ck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = clk_set_rate(b_ck, bck_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(afe->dev, "Failed to set b_ck rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct clk *m_ck, struct clk *b_ck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (m_ck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) clk_disable_unprepare(m_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (b_ck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clk_disable_unprepare(b_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (snd_soc_dai_active(dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (snd_soc_dai_active(dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mt8173_afe_set_i2s_enable(afe, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct snd_pcm_runtime * const runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct mt8173_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) runtime->rate * 256, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) runtime->rate * 256, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* config I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = mt8173_afe_set_i2s(afe, substream->runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mt8173_afe_set_i2s_enable(afe, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct mt8173_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (snd_soc_dai_active(dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) afe_priv->clocks[MT8173_CLK_I2S3_B]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct mt8173_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (snd_soc_dai_active(dai))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) afe_priv->clocks[MT8173_CLK_I2S3_B]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct snd_pcm_runtime * const runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct mt8173_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) runtime->rate * 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) afe_priv->clocks[MT8173_CLK_I2S3_B],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) runtime->rate * runtime->channels * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) val = AFE_TDM_CON1_BCK_INV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) AFE_TDM_CON1_LRCK_INV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) AFE_TDM_CON1_1_BCK_DELAY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) AFE_TDM_CON1_WLEN_32BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) AFE_TDM_CON1_32_BCK_CYCLES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) AFE_TDM_CON1_LRCK_WIDTH(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* set tdm2 config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) switch (runtime->channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) val = AFE_TDM_CH_START_O30_O31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val |= (AFE_TDM_CH_ZERO << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) val |= (AFE_TDM_CH_ZERO << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) val |= (AFE_TDM_CH_ZERO << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) val = AFE_TDM_CH_START_O30_O31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) val |= (AFE_TDM_CH_START_O32_O33 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val |= (AFE_TDM_CH_ZERO << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val |= (AFE_TDM_CH_ZERO << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) val = AFE_TDM_CH_START_O30_O31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val |= (AFE_TDM_CH_START_O32_O33 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val |= (AFE_TDM_CH_START_O34_O35 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) val |= (AFE_TDM_CH_ZERO << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) val = AFE_TDM_CH_START_O30_O31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) val |= (AFE_TDM_CH_START_O32_O33 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) val |= (AFE_TDM_CH_START_O34_O35 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) val |= (AFE_TDM_CH_START_O36_O37 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x000000f0, runtime->channels << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) regmap_write(afe->regmap, AFE_HDMI_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) AFE_HDMI_CONN0_O30_I30 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) AFE_HDMI_CONN0_O31_I31 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) AFE_HDMI_CONN0_O32_I34 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) AFE_HDMI_CONN0_O33_I35 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) AFE_HDMI_CONN0_O34_I32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) AFE_HDMI_CONN0_O35_I33 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) AFE_HDMI_CONN0_O36_I36 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) AFE_HDMI_CONN0_O37_I37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* enable Out control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* enable tdm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* disable tdm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* disable Out control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int mt8173_memif_fs(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct mtk_base_afe_memif *memif = &afe->memif[asoc_rtd_to_cpu(rtd, 0)->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (memif->data->id == MT8173_AFE_MEMIF_DAI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) fs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) fs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) fs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) fs = mt8173_afe_i2s_fs(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return mt8173_afe_i2s_fs(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* BE DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .startup = mt8173_afe_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .shutdown = mt8173_afe_i2s_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .prepare = mt8173_afe_i2s_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .startup = mt8173_afe_hdmi_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .shutdown = mt8173_afe_hdmi_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .prepare = mt8173_afe_hdmi_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .trigger = mt8173_afe_hdmi_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* FE DAIs: memory intefaces to CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .name = "DL1", /* downlink 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .id = MT8173_AFE_MEMIF_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .stream_name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = "VUL", /* voice uplink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .id = MT8173_AFE_MEMIF_VUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .stream_name = "VUL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* BE DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .name = "I2S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .id = MT8173_AFE_IO_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .stream_name = "I2S Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .stream_name = "I2S Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .ops = &mt8173_afe_i2s_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* FE DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .name = "HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .id = MT8173_AFE_MEMIF_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .stream_name = "HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SNDRV_PCM_RATE_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* BE DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .name = "HDMIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .id = MT8173_AFE_IO_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .stream_name = "HDMIO Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) SNDRV_PCM_RATE_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .ops = &mt8173_afe_hdmi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* inter-connections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {"I05", NULL, "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {"I06", NULL, "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {"I2S Playback", NULL, "O03"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {"I2S Playback", NULL, "O04"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {"VUL", NULL, "O09"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {"VUL", NULL, "O10"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {"I03", NULL, "I2S Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {"I04", NULL, "I2S Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {"I17", NULL, "I2S Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {"I18", NULL, "I2S Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { "O03", "I05 Switch", "I05" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { "O04", "I06 Switch", "I06" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { "O09", "I17 Switch", "I17" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { "O09", "I03 Switch", "I03" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { "O10", "I18 Switch", "I18" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { "O10", "I04 Switch", "I04" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {"HDMIO Playback", NULL, "HDMI"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .name = "mt8173-afe-pcm-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .dapm_widgets = mt8173_afe_pcm_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .dapm_routes = mt8173_afe_pcm_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .suspend = mtk_afe_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .resume = mtk_afe_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .name = "mt8173-afe-hdmi-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .dapm_routes = mt8173_afe_hdmi_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .suspend = mtk_afe_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .resume = mtk_afe_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const char *aud_clks[MT8173_CLK_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) [MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) [MT8173_CLK_I2S0_M] = "i2s0_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [MT8173_CLK_I2S1_M] = "i2s1_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [MT8173_CLK_I2S2_M] = "i2s2_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [MT8173_CLK_I2S3_M] = "i2s3_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [MT8173_CLK_I2S3_B] = "i2s3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [MT8173_CLK_BCK0] = "bck0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [MT8173_CLK_BCK1] = "bck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .id = MT8173_AFE_MEMIF_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .reg_ofs_base = AFE_DL1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .reg_ofs_cur = AFE_DL1_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .fs_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .mono_shift = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .hd_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .enable_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .msb_reg = AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .msb_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .name = "DL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .id = MT8173_AFE_MEMIF_DL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .reg_ofs_base = AFE_DL2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .reg_ofs_cur = AFE_DL2_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .fs_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .mono_shift = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .hd_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .enable_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .msb_reg = AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .msb_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .name = "VUL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .id = MT8173_AFE_MEMIF_VUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .reg_ofs_base = AFE_VUL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .reg_ofs_cur = AFE_VUL_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .fs_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .mono_shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .hd_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .enable_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .msb_reg = AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .msb_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .name = "DAI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .id = MT8173_AFE_MEMIF_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .reg_ofs_base = AFE_DAI_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .reg_ofs_cur = AFE_DAI_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .fs_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .fs_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .fs_maskbit = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .mono_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .mono_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .hd_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .enable_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .msb_reg = AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .msb_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .name = "AWB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .id = MT8173_AFE_MEMIF_AWB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .reg_ofs_base = AFE_AWB_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .reg_ofs_cur = AFE_AWB_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .fs_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .mono_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .hd_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .enable_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .msb_reg = AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .msb_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .name = "MOD_DAI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .id = MT8173_AFE_MEMIF_MOD_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .reg_ofs_base = AFE_MOD_PCM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .reg_ofs_cur = AFE_MOD_PCM_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .fs_shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .fs_maskbit = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .mono_shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .hd_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .enable_shift = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .msb_reg = AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .msb_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .name = "HDMI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .id = MT8173_AFE_MEMIF_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .reg_ofs_base = AFE_HDMI_OUT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .reg_ofs_cur = AFE_HDMI_OUT_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .fs_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .fs_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .fs_maskbit = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .mono_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .mono_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .hd_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .enable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .msb_reg = AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .msb_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .id = MT8173_AFE_IRQ_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .irq_cnt_reg = AFE_IRQ_CNT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .irq_en_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .irq_fs_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .irq_fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .irq_clr_reg = AFE_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .irq_clr_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .id = MT8173_AFE_IRQ_DL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .irq_cnt_reg = AFE_IRQ_CNT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .irq_cnt_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .irq_en_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .irq_fs_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .irq_fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .irq_clr_reg = AFE_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .irq_clr_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .id = MT8173_AFE_IRQ_VUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .irq_cnt_reg = AFE_IRQ_CNT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .irq_en_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .irq_fs_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .irq_fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .irq_clr_reg = AFE_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .irq_clr_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .id = MT8173_AFE_IRQ_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .irq_cnt_reg = AFE_IRQ_CNT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .irq_cnt_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .irq_en_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .irq_fs_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .irq_fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .irq_clr_reg = AFE_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .irq_clr_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .id = MT8173_AFE_IRQ_AWB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .irq_cnt_reg = AFE_IRQ_CNT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .irq_en_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .irq_fs_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .irq_fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .irq_clr_reg = AFE_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .irq_clr_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .id = MT8173_AFE_IRQ_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .irq_cnt_reg = AFE_IRQ_CNT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .irq_cnt_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .irq_en_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .irq_fs_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .irq_fs_maskbit = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .irq_clr_reg = AFE_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .irq_clr_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .id = MT8173_AFE_IRQ_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .irq_cnt_reg = AFE_IRQ_CNT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .irq_cnt_maskbit = 0x3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .irq_en_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .irq_fs_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .irq_fs_maskbit = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .irq_clr_reg = AFE_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .irq_clr_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const struct regmap_config mt8173_afe_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .max_register = AFE_ADDA2_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct mtk_base_afe *afe = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned int reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev_err(afe->dev, "%s irq status err\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) reg_value = AFE_IRQ_STATUS_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct mtk_base_afe_memif *memif = &afe->memif[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct mtk_base_afe_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (memif->irq_usage < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) irq = &afe->irqs[memif->irq_usage];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (!(reg_value & (1 << irq->irq_data->irq_clr_shift)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) snd_pcm_period_elapsed(memif->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* clear irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) regmap_write(afe->regmap, AFE_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) reg_value & AFE_IRQ_STATUS_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int mt8173_afe_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct mtk_base_afe *afe = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct mt8173_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* disable AFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* disable AFE clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int mt8173_afe_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct mtk_base_afe *afe = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct mt8173_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) goto err_infra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) goto err_top_aud_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto err_top_aud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) goto err_bck0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) goto err_i2s1_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) goto err_i2s2_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* enable AFE clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* set O3/O4 16bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* unmask all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* enable AFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) err_i2s1_m:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) err_i2s2_m:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) err_bck0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) err_top_aud:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) err_top_aud_bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) err_infra:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct mt8173_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (IS_ERR(afe_priv->clocks[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dev_err(afe->dev, "%s devm_clk_get %s fail\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) __func__, aud_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return PTR_ERR(afe_priv->clocks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int irq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct mtk_base_afe *afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct mt8173_afe_private *afe_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (!afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (!afe_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) afe->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) irq_id = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (irq_id <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return irq_id < 0 ? irq_id : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) 0, "Afe_ISR_Handle", (void *)afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev_err(afe->dev, "could not request_irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (IS_ERR(afe->base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return PTR_ERR(afe->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) &mt8173_afe_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (IS_ERR(afe->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return PTR_ERR(afe->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* initial audio related clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret = mt8173_afe_init_audio_clk(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) dev_err(afe->dev, "mt8173_afe_init_audio_clk fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* memif % irq initialize*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) afe->memif_size = MT8173_AFE_MEMIF_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) afe->memif = devm_kcalloc(afe->dev, afe->memif_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) sizeof(*afe->memif), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!afe->memif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) afe->irqs_size = MT8173_AFE_IRQ_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) sizeof(*afe->irqs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (!afe->irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) for (i = 0; i < afe->irqs_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) afe->memif[i].data = &memif_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) afe->irqs[i].irq_data = &irq_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) afe->irqs[i].irq_occupyed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) afe->memif[i].irq_usage = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) afe->memif[i].const_irq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) afe->mtk_afe_hardware = &mt8173_afe_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) afe->memif_fs = mt8173_memif_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) afe->irq_fs = mt8173_irq_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) platform_set_drvdata(pdev, afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret = mt8173_afe_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) afe->reg_back_up_list = mt8173_afe_backup_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) afe->runtime_resume = mt8173_afe_runtime_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) afe->runtime_suspend = mt8173_afe_runtime_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) &mtk_afe_pcm_platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) &mt8173_afe_pcm_dai_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) mt8173_afe_pcm_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ARRAY_SIZE(mt8173_afe_pcm_dais));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) &mt8173_afe_hdmi_dai_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) mt8173_afe_hdmi_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ARRAY_SIZE(mt8173_afe_hdmi_dais));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dev_info(&pdev->dev, "MT8173 AFE driver initialized.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static int mt8173_afe_pcm_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) mt8173_afe_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static const struct of_device_id mt8173_afe_pcm_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) { .compatible = "mediatek,mt8173-afe-pcm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static const struct dev_pm_ops mt8173_afe_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) SET_RUNTIME_PM_OPS(mt8173_afe_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) mt8173_afe_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static struct platform_driver mt8173_afe_pcm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .name = "mt8173-afe-pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .of_match_table = mt8173_afe_pcm_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .pm = &mt8173_afe_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .probe = mt8173_afe_pcm_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .remove = mt8173_afe_pcm_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) module_platform_driver(mt8173_afe_pcm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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