^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mt6797-reg.h -- Mediatek 6797 audio driver reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _MT6797_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _MT6797_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AUDIO_TOP_CON0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AUDIO_TOP_CON1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AUDIO_TOP_CON3 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AFE_DAC_CON0 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AFE_DAC_CON1 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AFE_I2S_CON 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AFE_DAIBT_CON0 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AFE_CONN0 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AFE_CONN1 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AFE_CONN2 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AFE_CONN3 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AFE_CONN4 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AFE_I2S_CON1 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AFE_I2S_CON2 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AFE_MRGIF_CON 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AFE_DL1_BASE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AFE_DL1_CUR 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AFE_DL1_END 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AFE_I2S_CON3 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AFE_DL2_BASE 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AFE_DL2_CUR 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AFE_DL2_END 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AFE_CONN5 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AFE_CONN_24BIT 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AFE_AWB_BASE 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AFE_AWB_END 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AFE_AWB_CUR 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AFE_VUL_BASE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AFE_VUL_END 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AFE_VUL_CUR 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AFE_DAI_BASE 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AFE_DAI_END 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AFE_DAI_CUR 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AFE_CONN6 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AFE_MEMIF_MSB 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AFE_MEMIF_MON0 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AFE_MEMIF_MON1 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AFE_MEMIF_MON2 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AFE_MEMIF_MON4 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AFE_ADDA_DL_SRC2_CON0 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AFE_ADDA_DL_SRC2_CON1 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AFE_ADDA_UL_SRC_CON0 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AFE_ADDA_UL_SRC_CON1 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AFE_ADDA_TOP_CON0 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AFE_ADDA_UL_DL_CON0 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AFE_ADDA_SRC_DEBUG 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AFE_ADDA_SRC_DEBUG_MON0 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AFE_ADDA_SRC_DEBUG_MON1 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AFE_ADDA_NEWIF_CFG0 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AFE_ADDA_NEWIF_CFG1 0x013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AFE_ADDA_NEWIF_CFG2 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AFE_DMA_CTL 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AFE_DMA_MON0 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AFE_DMA_MON1 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AFE_SIDETONE_DEBUG 0x01d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AFE_SIDETONE_MON 0x01d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AFE_SIDETONE_CON0 0x01e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AFE_SIDETONE_COEFF 0x01e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AFE_SIDETONE_CON1 0x01e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AFE_SIDETONE_GAIN 0x01ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AFE_SGEN_CON0 0x01f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AFE_SINEGEN_CON_TDM 0x01fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AFE_TOP_CON0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AFE_ADDA_PREDIS_CON0 0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AFE_ADDA_PREDIS_CON1 0x0264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AFE_MRGIF_MON0 0x0270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AFE_MRGIF_MON1 0x0274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AFE_MRGIF_MON2 0x0278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AFE_I2S_MON 0x027c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AFE_MOD_DAI_BASE 0x0330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AFE_MOD_DAI_END 0x0338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AFE_MOD_DAI_CUR 0x033c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AFE_VUL_D2_BASE 0x0350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AFE_VUL_D2_END 0x0358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AFE_VUL_D2_CUR 0x035c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AFE_DL3_BASE 0x0360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AFE_DL3_CUR 0x0364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AFE_DL3_END 0x0368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AFE_HDMI_OUT_CON0 0x0370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AFE_HDMI_BASE 0x0374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AFE_HDMI_CUR 0x0378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AFE_HDMI_END 0x037c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AFE_HDMI_CONN0 0x0390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AFE_IRQ3_MCU_CNT_MON 0x0398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AFE_IRQ4_MCU_CNT_MON 0x039c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AFE_IRQ_MCU_CON 0x03a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AFE_IRQ_MCU_STATUS 0x03a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AFE_IRQ_MCU_CLR 0x03a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AFE_IRQ_MCU_CNT1 0x03ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AFE_IRQ_MCU_CNT2 0x03b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AFE_IRQ_MCU_EN 0x03b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AFE_IRQ_MCU_MON2 0x03b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AFE_IRQ_MCU_CNT5 0x03bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AFE_IRQ1_MCU_CNT_MON 0x03c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AFE_IRQ2_MCU_CNT_MON 0x03c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AFE_IRQ5_MCU_CNT_MON 0x03cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AFE_MEMIF_MINLEN 0x03d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AFE_MEMIF_MAXLEN 0x03d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AFE_MEMIF_PBUF_SIZE 0x03d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AFE_IRQ_MCU_CNT7 0x03dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AFE_IRQ7_MCU_CNT_MON 0x03e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AFE_IRQ_MCU_CNT3 0x03e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AFE_IRQ_MCU_CNT4 0x03e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AFE_APLL1_TUNER_CFG 0x03f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AFE_APLL2_TUNER_CFG 0x03f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AFE_MEMIF_HD_MODE 0x03f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AFE_MEMIF_HDALIGN 0x03fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AFE_GAIN1_CON0 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AFE_GAIN1_CON1 0x0414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AFE_GAIN1_CON2 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AFE_GAIN1_CON3 0x041c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AFE_CONN7 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AFE_GAIN1_CUR 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AFE_GAIN2_CON0 0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AFE_GAIN2_CON1 0x042c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AFE_GAIN2_CON2 0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AFE_GAIN2_CON3 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AFE_CONN8 0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AFE_GAIN2_CUR 0x043c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AFE_CONN9 0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AFE_CONN10 0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AFE_CONN11 0x0448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AFE_CONN12 0x044c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AFE_CONN13 0x0450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AFE_CONN14 0x0454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AFE_CONN15 0x0458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AFE_CONN16 0x045c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AFE_CONN17 0x0460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AFE_CONN18 0x0464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AFE_CONN19 0x0468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AFE_CONN20 0x046c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AFE_CONN21 0x0470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AFE_CONN22 0x0474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AFE_CONN23 0x0478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AFE_CONN24 0x047c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AFE_CONN_RS 0x0494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AFE_CONN_DI 0x0498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AFE_CONN25 0x04b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AFE_CONN26 0x04b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AFE_CONN27 0x04b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AFE_CONN28 0x04bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AFE_CONN29 0x04c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AFE_SRAM_DELSEL_CON0 0x04f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AFE_SRAM_DELSEL_CON1 0x04f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AFE_ASRC_CON0 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AFE_ASRC_CON1 0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AFE_ASRC_CON2 0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AFE_ASRC_CON3 0x050c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AFE_ASRC_CON4 0x0510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AFE_ASRC_CON5 0x0514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AFE_ASRC_CON6 0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AFE_ASRC_CON7 0x051c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AFE_ASRC_CON8 0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AFE_ASRC_CON9 0x0524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AFE_ASRC_CON10 0x0528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AFE_ASRC_CON11 0x052c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PCM_INTF_CON1 0x0530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PCM_INTF_CON2 0x0538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PCM2_INTF_CON 0x053c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AFE_TDM_CON1 0x0548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AFE_TDM_CON2 0x054c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AFE_ASRC_CON13 0x0550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AFE_ASRC_CON14 0x0554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AFE_ASRC_CON15 0x0558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AFE_ASRC_CON16 0x055c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AFE_ASRC_CON17 0x0560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AFE_ASRC_CON18 0x0564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AFE_ASRC_CON19 0x0568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AFE_ASRC_CON20 0x056c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AFE_ASRC_CON21 0x0570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_AUDDIV_0 0x05a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_AUDDIV_1 0x05a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_AUDDIV_2 0x05a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_AUDDIV_3 0x05ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AUDIO_TOP_DBG_CON 0x05c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AUDIO_TOP_DBG_MON0 0x05cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AUDIO_TOP_DBG_MON1 0x05d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AUDIO_TOP_DBG_MON2 0x05d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AFE_ADDA2_TOP_CON0 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AFE_ASRC4_CON0 0x06c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AFE_ASRC4_CON1 0x06c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AFE_ASRC4_CON2 0x06c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AFE_ASRC4_CON3 0x06cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AFE_ASRC4_CON4 0x06d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AFE_ASRC4_CON5 0x06d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AFE_ASRC4_CON6 0x06d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AFE_ASRC4_CON7 0x06dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AFE_ASRC4_CON8 0x06e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AFE_ASRC4_CON9 0x06e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AFE_ASRC4_CON10 0x06e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AFE_ASRC4_CON11 0x06ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AFE_ASRC4_CON12 0x06f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AFE_ASRC4_CON13 0x06f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AFE_ASRC4_CON14 0x06f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AFE_ASRC2_CON0 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AFE_ASRC2_CON1 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AFE_ASRC2_CON2 0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AFE_ASRC2_CON3 0x070c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AFE_ASRC2_CON4 0x0710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AFE_ASRC2_CON5 0x0714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AFE_ASRC2_CON6 0x0718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AFE_ASRC2_CON7 0x071c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AFE_ASRC2_CON8 0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AFE_ASRC2_CON9 0x0724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AFE_ASRC2_CON10 0x0728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AFE_ASRC2_CON11 0x072c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AFE_ASRC2_CON12 0x0730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AFE_ASRC2_CON13 0x0734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AFE_ASRC2_CON14 0x0738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AFE_ASRC3_CON0 0x0740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AFE_ASRC3_CON1 0x0744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AFE_ASRC3_CON2 0x0748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AFE_ASRC3_CON3 0x074c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AFE_ASRC3_CON4 0x0750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AFE_ASRC3_CON5 0x0754
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AFE_ASRC3_CON6 0x0758
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AFE_ASRC3_CON7 0x075c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AFE_ASRC3_CON8 0x0760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AFE_ASRC3_CON9 0x0764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AFE_ASRC3_CON10 0x0768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AFE_ASRC3_CON11 0x076c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AFE_ASRC3_CON12 0x0770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AFE_ASRC3_CON13 0x0774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AFE_ASRC3_CON14 0x0778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AFE_GENERAL_REG0 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AFE_GENERAL_REG1 0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AFE_GENERAL_REG2 0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AFE_GENERAL_REG3 0x080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AFE_GENERAL_REG4 0x0810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define AFE_GENERAL_REG5 0x0814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AFE_GENERAL_REG6 0x0818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AFE_GENERAL_REG7 0x081c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AFE_GENERAL_REG8 0x0820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AFE_GENERAL_REG9 0x0824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AFE_GENERAL_REG10 0x0828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AFE_GENERAL_REG11 0x082c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AFE_GENERAL_REG12 0x0830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AFE_GENERAL_REG13 0x0834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AFE_GENERAL_REG14 0x0838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AFE_GENERAL_REG15 0x083c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AFE_CBIP_CFG0 0x0840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AFE_CBIP_MON0 0x0844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AFE_CBIP_SLV_MUX_MON0 0x0848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define AFE_CBIP_SLV_DECODER_MON0 0x084c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define AFE_MAX_REGISTER AFE_CBIP_SLV_DECODER_MON0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define AFE_IRQ_STATUS_BITS 0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* AUDIO_TOP_CON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define AHB_IDLE_EN_INT_SFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AHB_IDLE_EN_INT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define AHB_IDLE_EN_EXT_SFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define AHB_IDLE_EN_EXT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PDN_TML_SFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PDN_TML_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PDN_TML_MASK_SFT (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PDN_DAC_PREDIS_SFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define PDN_DAC_PREDIS_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define PDN_DAC_SFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PDN_DAC_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define PDN_DAC_MASK_SFT (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PDN_ADC_SFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PDN_ADC_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PDN_ADC_MASK_SFT (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PDN_TDM_CK_SFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PDN_TDM_CK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PDN_TDM_CK_MASK_SFT (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PDN_APLL_TUNER_SFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PDN_APLL_TUNER_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PDN_APLL_TUNER_MASK_SFT (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PDN_APLL2_TUNER_SFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PDN_APLL2_TUNER_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PDN_APLL2_TUNER_MASK_SFT (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define APB3_SEL_SFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define APB3_SEL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define APB3_SEL_MASK_SFT (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define APB_R2T_SFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define APB_R2T_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define APB_R2T_MASK_SFT (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define APB_W2T_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define APB_W2T_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define APB_W2T_MASK_SFT (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define PDN_24M_SFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PDN_24M_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PDN_24M_MASK_SFT (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PDN_22M_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PDN_22M_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define PDN_22M_MASK_SFT (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define PDN_ADDA4_ADC_SFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define PDN_ADDA4_ADC_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define PDN_ADDA4_ADC_MASK_SFT (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define PDN_I2S_SFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define PDN_I2S_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define PDN_I2S_MASK_SFT (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define PDN_AFE_SFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define PDN_AFE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define PDN_AFE_MASK_SFT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* AUDIO_TOP_CON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PDN_ADC_HIRES_TML_SFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define PDN_ADC_HIRES_TML_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define PDN_ADC_HIRES_TML_MASK_SFT (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PDN_ADC_HIRES_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PDN_ADC_HIRES_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define PDN_ADC_HIRES_MASK_SFT (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define I2S4_BCLK_SW_CG_SFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define I2S4_BCLK_SW_CG_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define I2S4_BCLK_SW_CG_MASK_SFT (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define I2S3_BCLK_SW_CG_SFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define I2S3_BCLK_SW_CG_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define I2S3_BCLK_SW_CG_MASK_SFT (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define I2S2_BCLK_SW_CG_SFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define I2S2_BCLK_SW_CG_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define I2S2_BCLK_SW_CG_MASK_SFT (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define I2S1_BCLK_SW_CG_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define I2S1_BCLK_SW_CG_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define I2S1_BCLK_SW_CG_MASK_SFT (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define I2S_SOFT_RST2_SFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define I2S_SOFT_RST2_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define I2S_SOFT_RST2_MASK_SFT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define I2S_SOFT_RST_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define I2S_SOFT_RST_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define I2S_SOFT_RST_MASK_SFT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* AFE_DAC_CON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define AFE_AWB_RETM_SFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define AFE_AWB_RETM_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define AFE_AWB_RETM_MASK_SFT (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define AFE_DL1_DATA2_RETM_SFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define AFE_DL1_DATA2_RETM_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define AFE_DL1_DATA2_RETM_MASK_SFT (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define AFE_DL2_RETM_SFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AFE_DL2_RETM_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define AFE_DL2_RETM_MASK_SFT (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define AFE_DL1_RETM_SFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define AFE_DL1_RETM_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define AFE_DL1_RETM_MASK_SFT (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define AFE_ON_RETM_SFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define AFE_ON_RETM_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define AFE_ON_RETM_MASK_SFT (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MOD_DAI_DUP_WR_SFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MOD_DAI_DUP_WR_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DAI_MODE_SFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DAI_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DAI_MODE_MASK_SFT (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define VUL_DATA2_MODE_SFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define VUL_DATA2_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define VUL_DATA2_MODE_MASK_SFT (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DL1_DATA2_MODE_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DL1_DATA2_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DL1_DATA2_MODE_MASK_SFT (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DL3_MODE_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DL3_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DL3_MODE_MASK_SFT (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define VUL_DATA2_R_MONO_SFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define VUL_DATA2_R_MONO_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define VUL_DATA2_R_MONO_MASK_SFT (0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define VUL_DATA2_DATA_SFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define VUL_DATA2_DATA_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define VUL_DATA2_DATA_MASK_SFT (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define VUL_DATA2_ON_SFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define VUL_DATA2_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define VUL_DATA2_ON_MASK_SFT (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define DL1_DATA2_ON_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define DL1_DATA2_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define DL1_DATA2_ON_MASK_SFT (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define MOD_DAI_ON_SFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define MOD_DAI_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define MOD_DAI_ON_MASK_SFT (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define AWB_ON_SFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define AWB_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define AWB_ON_MASK_SFT (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define DL3_ON_SFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DL3_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define DL3_ON_MASK_SFT (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define DAI_ON_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define DAI_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DAI_ON_MASK_SFT (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define VUL_ON_SFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define VUL_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define VUL_ON_MASK_SFT (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DL2_ON_SFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define DL2_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DL2_ON_MASK_SFT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define DL1_ON_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define DL1_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DL1_ON_MASK_SFT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define AFE_ON_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define AFE_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define AFE_ON_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* AFE_DAC_CON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define MOD_DAI_MODE_SFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define MOD_DAI_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define MOD_DAI_MODE_MASK_SFT (0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DAI_DUP_WR_SFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DAI_DUP_WR_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DAI_DUP_WR_MASK_SFT (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define VUL_R_MONO_SFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define VUL_R_MONO_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define VUL_R_MONO_MASK_SFT (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define VUL_DATA_SFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define VUL_DATA_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define VUL_DATA_MASK_SFT (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define AXI_2X1_CG_DISABLE_SFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define AXI_2X1_CG_DISABLE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define AXI_2X1_CG_DISABLE_MASK_SFT (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define AWB_R_MONO_SFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define AWB_R_MONO_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define AWB_R_MONO_MASK_SFT (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define AWB_DATA_SFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define AWB_DATA_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define AWB_DATA_MASK_SFT (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define DL3_DATA_SFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define DL3_DATA_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define DL3_DATA_MASK_SFT (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define DL2_DATA_SFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define DL2_DATA_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define DL2_DATA_MASK_SFT (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define DL1_DATA_SFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define DL1_DATA_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define DL1_DATA_MASK_SFT (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define DL1_DATA2_DATA_SFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define DL1_DATA2_DATA_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define DL1_DATA2_DATA_MASK_SFT (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define VUL_MODE_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define VUL_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define VUL_MODE_MASK_SFT (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define AWB_MODE_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define AWB_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define AWB_MODE_MASK_SFT (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define I2S_MODE_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define I2S_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define I2S_MODE_MASK_SFT (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define DL2_MODE_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define DL2_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define DL2_MODE_MASK_SFT (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define DL1_MODE_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define DL1_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define DL1_MODE_MASK_SFT (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* AFE_ADDA_DL_SRC2_CON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define DL_2_INPUT_MODE_CTL_SFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define DL_2_INPUT_MODE_CTL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define DL_2_CH1_SATURATION_EN_CTL_SFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define DL_2_CH2_SATURATION_EN_CTL_SFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define DL_2_OUTPUT_SEL_CTL_SFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define DL_2_OUTPUT_SEL_CTL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define DL_2_FADEIN_0START_EN_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define DL_2_FADEIN_0START_EN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define DL_DISABLE_HW_CG_CTL_SFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define DL_DISABLE_HW_CG_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define C_DATA_EN_SEL_CTL_PRE_SFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define DL2_ARAMPSP_CTL_PRE_SFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DL2_ARAMPSP_CTL_PRE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define DL_2_IIRMODE_CTL_PRE_SFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DL_2_IIRMODE_CTL_PRE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DL_2_VOICE_MODE_CTL_PRE_SFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define DL_2_IIR_ON_CTL_PRE_SFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define DL_2_IIR_ON_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define DL_2_GAIN_ON_CTL_PRE_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* AFE_ADDA_DL_SRC2_CON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define DL_2_GAIN_CTL_PRE_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define DL_2_GAIN_CTL_PRE_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define DL_2_GAIN_MODE_CTL_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define DL_2_GAIN_MODE_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* AFE_ADDA_UL_SRC_CON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define C_COMB_OUT_SIN_GEN_CTL_SFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define C_COMB_OUT_SIN_GEN_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define C_COMB_OUT_SIN_GEN_CTL_MASK_SFT (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define C_BASEBAND_SIN_GEN_CTL_SFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define C_BASEBAND_SIN_GEN_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define C_BASEBAND_SIN_GEN_CTL_MASK_SFT (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define C_TWO_DIGITAL_MIC_CTL_SFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define UL_MODE_3P25M_CH2_CTL_SFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define UL_MODE_3P25M_CH2_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define UL_MODE_3P25M_CH1_CTL_SFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define UL_MODE_3P25M_CH1_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define UL_SRC_USE_CIC_OUT_CTL_SFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define UL_SRC_USE_CIC_OUT_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define UL_SRC_USE_CIC_OUT_CTL_MASK_SFT (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define DMIC_LOW_POWER_MODE_CTL_SFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define DMIC_48K_SEL_CTL_SFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define DMIC_48K_SEL_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define DMIC_48K_SEL_CTL_MASK_SFT (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define UL_DISABLE_HW_CG_CTL_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define UL_DISABLE_HW_CG_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define UL_IIR_ON_TMP_CTL_SFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define UL_IIR_ON_TMP_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define UL_IIRMODE_CTL_SFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define UL_IIRMODE_CTL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define AGC_260K_SEL_CH2_CTL_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define AGC_260K_SEL_CH2_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define AGC_260K_SEL_CH2_CTL_MASK_SFT (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define AGC_260K_SEL_CH1_CTL_SFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define AGC_260K_SEL_CH1_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define AGC_260K_SEL_CH1_CTL_MASK_SFT (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define UL_LOOP_BACK_MODE_CTL_SFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define UL_SDM_3_LEVEL_CTL_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define UL_SDM_3_LEVEL_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define UL_SRC_ON_TMP_CTL_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define UL_SRC_ON_TMP_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* AFE_ADDA_UL_SRC_CON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define C_SDM_RESET_CTL_SFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define C_SDM_RESET_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define C_SDM_RESET_CTL_MASK_SFT (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define ADITHON_CTL_SFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define ADITHON_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define ADITHON_CTL_MASK_SFT (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define ADITHVAL_CTL_SFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define ADITHVAL_CTL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define ADITHVAL_CTL_MASK_SFT (0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define C_DAC_EN_CTL_SFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define C_DAC_EN_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define C_MUTE_SW_CTL_SFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define C_MUTE_SW_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define ASDM_SRC_SEL_CTL_SFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define ASDM_SRC_SEL_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define C_AMP_DIV_CH2_CTL_SFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define C_AMP_DIV_CH2_CTL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define C_FREQ_DIV_CH2_CTL_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define C_FREQ_DIV_CH2_CTL_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define C_SINE_MODE_CH2_CTL_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define C_SINE_MODE_CH2_CTL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define C_AMP_DIV_CH1_CTL_SFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define C_AMP_DIV_CH1_CTL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define C_FREQ_DIV_CH1_CTL_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define C_FREQ_DIV_CH1_CTL_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define C_SINE_MODE_CH1_CTL_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define C_SINE_MODE_CH1_CTL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* AFE_ADDA_TOP_CON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define C_LOOP_BACK_MODE_CTL_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define C_LOOP_BACK_MODE_CTL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define C_EXT_ADC_CTL_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define C_EXT_ADC_CTL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* AFE_ADDA_UL_DL_CON0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define AFE_UL_DL_CON0_RESERVED_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define AFE_UL_DL_CON0_RESERVED_MASK 0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define AFE_UL_DL_CON0_RESERVED_MASK_SFT (0x3fff << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define ADDA_AFE_ON_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define ADDA_AFE_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define ADDA_AFE_ON_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* AFE_IRQ_MCU_CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define IRQ7_MCU_MODE_SFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define IRQ7_MCU_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define IRQ7_MCU_MODE_MASK_SFT (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define IRQ4_MCU_MODE_SFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define IRQ4_MCU_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define IRQ4_MCU_MODE_MASK_SFT (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define IRQ3_MCU_MODE_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define IRQ3_MCU_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define IRQ3_MCU_MODE_MASK_SFT (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define IRQ7_MCU_ON_SFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define IRQ7_MCU_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define IRQ7_MCU_ON_MASK_SFT (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define IRQ5_MCU_ON_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define IRQ5_MCU_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define IRQ5_MCU_ON_MASK_SFT (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define IRQ2_MCU_MODE_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define IRQ2_MCU_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define IRQ2_MCU_MODE_MASK_SFT (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define IRQ1_MCU_MODE_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define IRQ1_MCU_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define IRQ1_MCU_MODE_MASK_SFT (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define IRQ4_MCU_ON_SFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define IRQ4_MCU_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define IRQ4_MCU_ON_MASK_SFT (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define IRQ3_MCU_ON_SFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define IRQ3_MCU_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define IRQ3_MCU_ON_MASK_SFT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define IRQ2_MCU_ON_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define IRQ2_MCU_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define IRQ2_MCU_ON_MASK_SFT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define IRQ1_MCU_ON_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define IRQ1_MCU_ON_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define IRQ1_MCU_ON_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* AFE_IRQ_MCU_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define AFE_IRQ_CM4_EN_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define AFE_IRQ_CM4_EN_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define AFE_IRQ_CM4_EN_MASK_SFT (0x7f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define AFE_IRQ_MD32_EN_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define AFE_IRQ_MD32_EN_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define AFE_IRQ_MD32_EN_MASK_SFT (0x7f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define AFE_IRQ_MCU_EN_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define AFE_IRQ_MCU_EN_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define AFE_IRQ_MCU_EN_MASK_SFT (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* AFE_IRQ_MCU_CLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define IRQ7_MCU_CLR_SFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define IRQ7_MCU_CLR_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define IRQ5_MCU_CLR_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define IRQ5_MCU_CLR_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define IRQ4_MCU_CLR_SFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define IRQ4_MCU_CLR_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define IRQ3_MCU_CLR_SFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define IRQ3_MCU_CLR_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define IRQ2_MCU_CLR_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define IRQ2_MCU_CLR_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define IRQ1_MCU_CLR_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define IRQ1_MCU_CLR_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* AFE_IRQ_MCU_CNT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define AFE_IRQ_MCU_CNT1_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define AFE_IRQ_MCU_CNT1_MASK 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define AFE_IRQ_MCU_CNT1_MASK_SFT (0x3ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* AFE_IRQ_MCU_CNT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define AFE_IRQ_MCU_CNT2_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define AFE_IRQ_MCU_CNT2_MASK 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define AFE_IRQ_MCU_CNT2_MASK_SFT (0x3ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* AFE_IRQ_MCU_CNT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define AFE_IRQ_MCU_CNT3_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define AFE_IRQ_MCU_CNT3_MASK 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define AFE_IRQ_MCU_CNT3_MASK_SFT (0x3ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* AFE_IRQ_MCU_CNT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define AFE_IRQ_MCU_CNT4_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define AFE_IRQ_MCU_CNT4_MASK 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define AFE_IRQ_MCU_CNT4_MASK_SFT (0x3ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* AFE_IRQ_MCU_CNT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define AFE_IRQ_MCU_CNT5_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define AFE_IRQ_MCU_CNT5_MASK 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define AFE_IRQ_MCU_CNT5_MASK_SFT (0x3ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* AFE_IRQ_MCU_CNT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define AFE_IRQ_MCU_CNT7_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define AFE_IRQ_MCU_CNT7_MASK 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define AFE_IRQ_MCU_CNT7_MASK_SFT (0x3ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* AFE_MEMIF_MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define CPU_COMPACT_MODE_SFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define CPU_COMPACT_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define CPU_HD_ALIGN_SFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define CPU_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define CPU_HD_ALIGN_MASK_SFT (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* AFE_MEMIF_HD_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define HDMI_HD_SFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define HDMI_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define HDMI_HD_MASK_SFT (0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define MOD_DAI_HD_SFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define MOD_DAI_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define MOD_DAI_HD_MASK_SFT (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define DAI_HD_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define DAI_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define DAI_HD_MASK_SFT (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define VUL_DATA2_HD_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define VUL_DATA2_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define VUL_DATA2_HD_MASK_SFT (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define VUL_HD_SFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define VUL_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define VUL_HD_MASK_SFT (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define AWB_HD_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define AWB_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define AWB_HD_MASK_SFT (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define DL3_HD_SFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define DL3_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define DL3_HD_MASK_SFT (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define DL2_HD_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define DL2_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define DL2_HD_MASK_SFT (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define DL1_DATA2_HD_SFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define DL1_DATA2_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define DL1_DATA2_HD_MASK_SFT (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define DL1_HD_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define DL1_HD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define DL1_HD_MASK_SFT (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* AFE_MEMIF_HDALIGN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define HDMI_NORMAL_MODE_SFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define HDMI_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define MOD_DAI_NORMAL_MODE_SFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define MOD_DAI_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define DAI_NORMAL_MODE_SFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define DAI_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define VUL_DATA2_NORMAL_MODE_SFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define VUL_DATA2_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define VUL_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define VUL_NORMAL_MODE_SFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define VUL_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define AWB_NORMAL_MODE_SFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define AWB_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define DL3_NORMAL_MODE_SFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define DL3_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define DL2_NORMAL_MODE_SFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define DL2_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define DL1_DATA2_NORMAL_MODE_SFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define DL1_DATA2_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define DL1_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define DL1_NORMAL_MODE_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define DL1_NORMAL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define HDMI_HD_ALIGN_SFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define HDMI_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define MOD_DAI_HD_ALIGN_SFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define MOD_DAI_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define DAI_ALIGN_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define DAI_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define DAI_ALIGN_MASK_SFT (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define VUL2_HD_ALIGN_SFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define VUL2_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define VUL_DATA2_HD_ALIGN_SFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define VUL_DATA2_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define VUL_DATA2_HD_ALIGN_MASK_SFT (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define VUL_HD_ALIGN_SFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define VUL_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define VUL_HD_ALIGN_MASK_SFT (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define AWB_HD_ALIGN_SFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define AWB_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define AWB_HD_ALIGN_MASK_SFT (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define DL3_HD_ALIGN_SFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define DL3_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define DL3_HD_ALIGN_MASK_SFT (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define DL2_HD_ALIGN_SFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define DL2_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define DL2_HD_ALIGN_MASK_SFT (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define DL1_DATA2_HD_ALIGN_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define DL1_DATA2_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define DL1_DATA2_HD_ALIGN_MASK_SFT (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define DL1_HD_ALIGN_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define DL1_HD_ALIGN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define DL1_HD_ALIGN_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* PCM_INTF_CON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define PCM_FIX_VALUE_SEL_SFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define PCM_FIX_VALUE_SEL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define PCM_BUFFER_LOOPBACK_SFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define PCM_BUFFER_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define PCM_PARALLEL_LOOPBACK_SFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define PCM_PARALLEL_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define PCM_SERIAL_LOOPBACK_SFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define PCM_SERIAL_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define PCM_DAI_PCM_LOOPBACK_SFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define PCM_DAI_PCM_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define PCM_I2S_PCM_LOOPBACK_SFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define PCM_I2S_PCM_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define PCM_SYNC_DELSEL_SFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define PCM_SYNC_DELSEL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define PCM_TX_LR_SWAP_SFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define PCM_TX_LR_SWAP_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define PCM_SYNC_OUT_INV_SFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define PCM_SYNC_OUT_INV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define PCM_BCLK_OUT_INV_SFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define PCM_BCLK_OUT_INV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define PCM_SYNC_IN_INV_SFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define PCM_SYNC_IN_INV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define PCM_BCLK_IN_INV_SFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define PCM_BCLK_IN_INV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define PCM_TX_LCH_RPT_SFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define PCM_TX_LCH_RPT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define PCM_VBT_16K_MODE_SFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define PCM_VBT_16K_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define PCM_EXT_MODEM_SFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define PCM_EXT_MODEM_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define PCM_24BIT_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define PCM_24BIT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define PCM_24BIT_MASK_SFT (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define PCM_WLEN_SFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define PCM_WLEN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define PCM_WLEN_MASK_SFT (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define PCM_SYNC_LENGTH_SFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define PCM_SYNC_LENGTH_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define PCM_SYNC_TYPE_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define PCM_SYNC_TYPE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define PCM_BT_MODE_SFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define PCM_BT_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define PCM_BT_MODE_MASK_SFT (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define PCM_BYP_ASRC_SFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define PCM_BYP_ASRC_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define PCM_SLAVE_SFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define PCM_SLAVE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define PCM_SLAVE_MASK_SFT (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define PCM_MODE_SFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define PCM_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define PCM_MODE_MASK_SFT (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define PCM_FMT_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define PCM_FMT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define PCM_FMT_MASK_SFT (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define PCM_EN_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define PCM_EN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define PCM_EN_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* PCM_INTF_CON2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define PCM1_TX_FIFO_OV_SFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define PCM1_TX_FIFO_OV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define PCM1_RX_FIFO_OV_SFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define PCM1_RX_FIFO_OV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define PCM2_TX_FIFO_OV_SFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define PCM2_TX_FIFO_OV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define PCM2_RX_FIFO_OV_SFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define PCM2_RX_FIFO_OV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define PCM1_SYNC_GLITCH_SFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define PCM1_SYNC_GLITCH_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define PCM2_SYNC_GLITCH_SFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define PCM2_SYNC_GLITCH_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define PCM1_PCM2_LOOPBACK_SFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define PCM1_PCM2_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define DAI_PCM_LOOPBACK_CH_SFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define DAI_PCM_LOOPBACK_CH_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define I2S_PCM_LOOPBACK_CH_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define I2S_PCM_LOOPBACK_CH_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define PCM_USE_MD3_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define PCM_USE_MD3_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define PCM_USE_MD3_MASK_SFT (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define TX_FIX_VALUE_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define TX_FIX_VALUE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define TX_FIX_VALUE_MASK_SFT (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* PCM2_INTF_CON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define PCM2_TX_FIX_VALUE_SFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define PCM2_TX_FIX_VALUE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define PCM2_FIX_VALUE_SEL_SFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define PCM2_FIX_VALUE_SEL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define PCM2_BUFFER_LOOPBACK_SFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define PCM2_BUFFER_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define PCM2_PARALLEL_LOOPBACK_SFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define PCM2_PARALLEL_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define PCM2_SERIAL_LOOPBACK_SFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define PCM2_SERIAL_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define PCM2_DAI_PCM_LOOPBACK_SFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define PCM2_DAI_PCM_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define PCM2_I2S_PCM_LOOPBACK_SFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define PCM2_I2S_PCM_LOOPBACK_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define PCM2_SYNC_DELSEL_SFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define PCM2_SYNC_DELSEL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define PCM2_TX_LR_SWAP_SFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define PCM2_TX_LR_SWAP_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define PCM2_SYNC_IN_INV_SFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define PCM2_SYNC_IN_INV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define PCM2_BCLK_IN_INV_SFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define PCM2_BCLK_IN_INV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define PCM2_TX_LCH_RPT_SFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define PCM2_TX_LCH_RPT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define PCM2_VBT_16K_MODE_SFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define PCM2_VBT_16K_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define PCM2_LOOPBACK_CH_SEL_SFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define PCM2_LOOPBACK_CH_SEL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define PCM2_TX2_BT_MODE_SFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define PCM2_TX2_BT_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define PCM2_BT_MODE_SFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define PCM2_BT_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define PCM2_BT_MODE_MASK_SFT (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define PCM2_AFIFO_SFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define PCM2_AFIFO_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define PCM2_AFIFO_MASK_SFT (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define PCM2_WLEN_SFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define PCM2_WLEN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define PCM2_WLEN_MASK_SFT (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define PCM2_MODE_SFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define PCM2_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define PCM2_MODE_MASK_SFT (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define PCM2_FMT_SFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define PCM2_FMT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define PCM2_FMT_MASK_SFT (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define PCM2_EN_SFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define PCM2_EN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define PCM2_EN_MASK_SFT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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