^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // MediaTek ALSA SoC Audio DAI ADDA Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "mt6797-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "mt6797-interconnection.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "mt6797-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) MTK_AFE_ADDA_DL_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MTK_AFE_ADDA_DL_RATE_11K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MTK_AFE_ADDA_DL_RATE_12K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MTK_AFE_ADDA_DL_RATE_16K = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MTK_AFE_ADDA_DL_RATE_22K = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MTK_AFE_ADDA_DL_RATE_24K = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MTK_AFE_ADDA_DL_RATE_32K = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MTK_AFE_ADDA_DL_RATE_44K = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MTK_AFE_ADDA_DL_RATE_48K = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MTK_AFE_ADDA_DL_RATE_96K = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MTK_AFE_ADDA_DL_RATE_192K = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MTK_AFE_ADDA_UL_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MTK_AFE_ADDA_UL_RATE_16K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MTK_AFE_ADDA_UL_RATE_32K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MTK_AFE_ADDA_UL_RATE_48K = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MTK_AFE_ADDA_UL_RATE_96K = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MTK_AFE_ADDA_UL_RATE_192K = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return MTK_AFE_ADDA_DL_RATE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return MTK_AFE_ADDA_DL_RATE_11K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case 12000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return MTK_AFE_ADDA_DL_RATE_12K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return MTK_AFE_ADDA_DL_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return MTK_AFE_ADDA_DL_RATE_22K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case 24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return MTK_AFE_ADDA_DL_RATE_24K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return MTK_AFE_ADDA_DL_RATE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return MTK_AFE_ADDA_DL_RATE_44K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return MTK_AFE_ADDA_DL_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return MTK_AFE_ADDA_DL_RATE_96K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return MTK_AFE_ADDA_DL_RATE_192K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return MTK_AFE_ADDA_DL_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return MTK_AFE_ADDA_UL_RATE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return MTK_AFE_ADDA_UL_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return MTK_AFE_ADDA_UL_RATE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return MTK_AFE_ADDA_UL_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return MTK_AFE_ADDA_UL_RATE_96K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return MTK_AFE_ADDA_UL_RATE_192K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return MTK_AFE_ADDA_UL_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* dai component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) I_PCM_1_CAP_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) I_PCM_2_CAP_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) I_PCM_1_CAP_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) I_PCM_2_CAP_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) I_PCM_1_CAP_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) I_PCM_2_CAP_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __func__, w->name, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case SND_SOC_DAPM_POST_PMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) usleep_range(125, 135);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SUPPLY_SEQ_AUD_TOP_PDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SUPPLY_SEQ_ADDA_AFE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SUPPLY_SEQ_ADDA_DL_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SUPPLY_SEQ_ADDA_UL_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* adda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mtk_adda_dl_ch1_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mtk_adda_dl_ch2_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) AFE_ADDA_DL_SRC2_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) AFE_ADDA_UL_SRC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) UL_SRC_ON_TMP_CTL_SFT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mtk_adda_ul_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SND_SOC_DAPM_POST_PMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SND_SOC_DAPM_SUPPLY_S("aud_dac_clk", SUPPLY_SEQ_AUD_TOP_PDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) AUDIO_TOP_CON0, PDN_DAC_SFT, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SND_SOC_DAPM_SUPPLY_S("aud_dac_predis_clk", SUPPLY_SEQ_AUD_TOP_PDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) AUDIO_TOP_CON0, PDN_DAC_PREDIS_SFT, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SND_SOC_DAPM_SUPPLY_S("aud_adc_clk", SUPPLY_SEQ_AUD_TOP_PDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) AUDIO_TOP_CON0, PDN_ADC_SFT, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {"ADDA Playback", NULL, "ADDA_DL_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {"ADDA Playback", NULL, "ADDA_DL_CH2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* adda enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {"ADDA Playback", NULL, "ADDA Enable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {"ADDA Playback", NULL, "ADDA Playback Enable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {"ADDA Capture", NULL, "ADDA Enable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {"ADDA Capture", NULL, "ADDA Capture Enable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {"ADDA Playback", NULL, "mtkaif_26m_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {"ADDA Playback", NULL, "aud_dac_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {"ADDA Playback", NULL, "aud_dac_predis_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {"ADDA Capture", NULL, "mtkaif_26m_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {"ADDA Capture", NULL, "aud_adc_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* dai ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __func__, dai->id, substream->stream, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int dl_src2_con0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int dl_src2_con1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* clean predistortion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* set input sampling rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* set output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dl_src2_con0 |= 1 << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dl_src2_con0 |= 1 << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* turn off mute function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dl_src2_con0 |= (0x03 << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* set voice input data if input sample rate is 8k or 16k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (rate == 8000 || rate == 16000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dl_src2_con0 |= 0x01 << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (rate < 96000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* SA suggest apply -0.3db to audio/speech path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dl_src2_con1 = 0xf74f0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* SA suggest apply -0.3db to audio/speech path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * with DL gain set to half,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * 0xFFFF = 0dB -> 0x8000 = 0dB when 96k, 192k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dl_src2_con1 = 0x7ba70000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* turn on down-link gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int voice_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int ul_src_con0 = 0; /* default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Using Internal ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) AFE_ADDA_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x0 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) voice_mode = adda_ul_rate_transform(afe, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* up8x txif sat on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) regmap_write(afe->regmap, AFE_ADDA_NEWIF_CFG0, 0x03F87201);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (rate >= 96000) { /* hires */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* use hires format [1 0 23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) AFE_ADDA_NEWIF_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0x1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) AFE_ADDA_NEWIF_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0xf << 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) voice_mode << 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else { /* normal 8~48k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* use fixed 260k anc path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) AFE_ADDA_NEWIF_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0xf << 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 8 << 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* ul_use_cic_out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ul_src_con0 |= 0x1 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) AFE_ADDA_NEWIF_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0xf << 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 8 << 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) AFE_ADDA_UL_SRC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0xfffffffe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ul_src_con0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .hw_params = mtk_dai_adda_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* dai driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SNDRV_PCM_RATE_96000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SNDRV_PCM_RATE_16000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SNDRV_PCM_RATE_32000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) SNDRV_PCM_RATE_48000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SNDRV_PCM_RATE_96000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SNDRV_PCM_FMTBIT_S24_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "ADDA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .id = MT6797_DAI_ADDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .stream_name = "ADDA Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .rates = MTK_ADDA_PLAYBACK_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .formats = MTK_ADDA_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .stream_name = "ADDA Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .rates = MTK_ADDA_CAPTURE_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .formats = MTK_ADDA_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .ops = &mtk_dai_adda_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int mt6797_dai_adda_register(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct mtk_base_afe_dai *dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) list_add(&dai->list, &afe->sub_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dai->dai_drivers = mtk_dai_adda_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dai->dapm_widgets = mtk_dai_adda_widgets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dai->dapm_routes = mtk_dai_adda_routes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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