^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Mediatek ALSA SoC AFE platform driver for 6797
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "mt6797-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "mt6797-afe-clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "mt6797-interconnection.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "mt6797-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "../common/mtk-afe-platform-driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../common/mtk-afe-fe-dai.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MTK_AFE_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MTK_AFE_RATE_11K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MTK_AFE_RATE_12K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MTK_AFE_RATE_384K = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MTK_AFE_RATE_16K = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MTK_AFE_RATE_22K = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MTK_AFE_RATE_24K = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MTK_AFE_RATE_130K = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MTK_AFE_RATE_32K = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MTK_AFE_RATE_44K = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MTK_AFE_RATE_48K = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MTK_AFE_RATE_88K = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MTK_AFE_RATE_96K = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MTK_AFE_RATE_174K = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MTK_AFE_RATE_192K = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MTK_AFE_RATE_260K = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MTK_AFE_DAI_MEMIF_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MTK_AFE_DAI_MEMIF_RATE_16K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MTK_AFE_DAI_MEMIF_RATE_32K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MTK_AFE_PCM_RATE_8K = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MTK_AFE_PCM_RATE_16K = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MTK_AFE_PCM_RATE_32K = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MTK_AFE_PCM_RATE_48K = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int mt6797_general_rate_transform(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return MTK_AFE_RATE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 11025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return MTK_AFE_RATE_11K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case 12000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return MTK_AFE_RATE_12K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return MTK_AFE_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 22050:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return MTK_AFE_RATE_22K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case 24000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return MTK_AFE_RATE_24K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return MTK_AFE_RATE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return MTK_AFE_RATE_44K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return MTK_AFE_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 88200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return MTK_AFE_RATE_88K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return MTK_AFE_RATE_96K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case 130000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return MTK_AFE_RATE_130K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case 176400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return MTK_AFE_RATE_174K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return MTK_AFE_RATE_192K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case 260000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return MTK_AFE_RATE_260K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __func__, rate, MTK_AFE_RATE_48K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return MTK_AFE_RATE_48K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static unsigned int dai_memif_rate_transform(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return MTK_AFE_DAI_MEMIF_RATE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return MTK_AFE_DAI_MEMIF_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return MTK_AFE_DAI_MEMIF_RATE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return MTK_AFE_DAI_MEMIF_RATE_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int mt6797_rate_transform(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int rate, int aud_blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (aud_blk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case MT6797_MEMIF_DAI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case MT6797_MEMIF_MOD_DAI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return dai_memif_rate_transform(dev, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return mt6797_general_rate_transform(dev, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct snd_pcm_hardware mt6797_afe_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SNDRV_PCM_INFO_MMAP_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SNDRV_PCM_FMTBIT_S24_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .period_bytes_min = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .period_bytes_max = 4 * 48 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .periods_max = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .buffer_bytes_max = 8 * 48 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int mt6797_memif_fs(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct snd_soc_component *component =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int id = asoc_rtd_to_cpu(rtd, 0)->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return mt6797_rate_transform(afe->dev, rate, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int mt6797_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct snd_soc_component *component =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return mt6797_general_rate_transform(afe->dev, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SNDRV_PCM_RATE_88200 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SNDRV_PCM_RATE_96000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SNDRV_PCM_RATE_176400 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SNDRV_PCM_RATE_192000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SNDRV_PCM_RATE_16000 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SNDRV_PCM_RATE_32000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SNDRV_PCM_FMTBIT_S24_LE |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct snd_soc_dai_driver mt6797_memif_dai_driver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* FE DAIs: memory intefaces to CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .id = MT6797_MEMIF_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .stream_name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .name = "DL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .id = MT6797_MEMIF_DL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .stream_name = "DL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "DL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .id = MT6797_MEMIF_DL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .stream_name = "DL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = "UL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .id = MT6797_MEMIF_VUL12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .stream_name = "UL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "UL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .id = MT6797_MEMIF_AWB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .stream_name = "UL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .name = "UL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .id = MT6797_MEMIF_VUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .stream_name = "UL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .rates = MTK_PCM_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "UL_MONO_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .id = MT6797_MEMIF_MOD_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .stream_name = "UL_MONO_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .rates = MTK_PCM_DAI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "UL_MONO_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .id = MT6797_MEMIF_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .stream_name = "UL_MONO_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .rates = MTK_PCM_DAI_RATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .formats = MTK_PCM_FORMATS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .ops = &mtk_afe_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* dma widget & routes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) I_DL1_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) I_DL2_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) I_DL3_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) I_DL1_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) I_DL2_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) I_DL3_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct snd_kcontrol_new memif_ul_mono_2_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) I_ADDA_UL_CH1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) I_ADDA_UL_CH2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct snd_soc_dapm_widget mt6797_memif_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* memif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) memif_ul_mono_1_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ARRAY_SIZE(memif_ul_mono_1_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SND_SOC_DAPM_MIXER("UL_MONO_2_CH1", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) memif_ul_mono_2_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ARRAY_SIZE(memif_ul_mono_2_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct snd_soc_dapm_route mt6797_memif_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {"UL1", NULL, "UL1_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {"UL1", NULL, "UL1_CH2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {"UL2", NULL, "UL2_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {"UL2", NULL, "UL2_CH2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {"UL3", NULL, "UL3_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {"UL3", NULL, "UL3_CH2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {"UL_MONO_2", NULL, "UL_MONO_2_CH1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {"UL_MONO_2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {"UL_MONO_2_CH1", "ADDA_UL_CH2", "ADDA Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct snd_soc_component_driver mt6797_afe_pcm_dai_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "mt6797-afe-pcm-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [MT6797_MEMIF_DL1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .id = MT6797_MEMIF_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .reg_ofs_base = AFE_DL1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .reg_ofs_cur = AFE_DL1_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .fs_shift = DL1_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .fs_maskbit = DL1_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .mono_shift = DL1_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .enable_shift = DL1_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .hd_shift = DL1_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [MT6797_MEMIF_DL2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .name = "DL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .id = MT6797_MEMIF_DL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .reg_ofs_base = AFE_DL2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .reg_ofs_cur = AFE_DL2_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .fs_shift = DL2_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .fs_maskbit = DL2_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .mono_shift = DL2_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .enable_shift = DL2_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .hd_shift = DL2_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [MT6797_MEMIF_DL3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = "DL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .id = MT6797_MEMIF_DL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .reg_ofs_base = AFE_DL3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .reg_ofs_cur = AFE_DL3_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .fs_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .fs_shift = DL3_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .fs_maskbit = DL3_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .mono_shift = DL3_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .enable_shift = DL3_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .hd_shift = DL3_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [MT6797_MEMIF_VUL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .name = "VUL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .id = MT6797_MEMIF_VUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .reg_ofs_base = AFE_VUL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .reg_ofs_cur = AFE_VUL_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .fs_shift = VUL_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .fs_maskbit = VUL_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .mono_shift = VUL_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .enable_shift = VUL_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .hd_shift = VUL_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) [MT6797_MEMIF_AWB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .name = "AWB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .id = MT6797_MEMIF_AWB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .reg_ofs_base = AFE_AWB_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .reg_ofs_cur = AFE_AWB_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .fs_shift = AWB_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .fs_maskbit = AWB_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .mono_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .mono_shift = AWB_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .enable_shift = AWB_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .hd_shift = AWB_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) [MT6797_MEMIF_VUL12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .name = "VUL12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .id = MT6797_MEMIF_VUL12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .reg_ofs_base = AFE_VUL_D2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .reg_ofs_cur = AFE_VUL_D2_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .fs_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .fs_shift = VUL_DATA2_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .fs_maskbit = VUL_DATA2_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .mono_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .mono_shift = VUL_DATA2_DATA_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .enable_shift = VUL_DATA2_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .hd_shift = VUL_DATA2_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [MT6797_MEMIF_DAI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = "DAI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .id = MT6797_MEMIF_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .reg_ofs_base = AFE_DAI_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .reg_ofs_cur = AFE_DAI_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .fs_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .fs_shift = DAI_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .fs_maskbit = DAI_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .mono_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .mono_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .enable_shift = DAI_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .hd_shift = DAI_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [MT6797_MEMIF_MOD_DAI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .name = "MOD_DAI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .id = MT6797_MEMIF_MOD_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .reg_ofs_base = AFE_MOD_DAI_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .reg_ofs_cur = AFE_MOD_DAI_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .fs_shift = MOD_DAI_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .fs_maskbit = MOD_DAI_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .mono_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .mono_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .enable_shift = MOD_DAI_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .hd_reg = AFE_MEMIF_HD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .hd_shift = MOD_DAI_HD_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .agent_disable_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const struct mtk_base_irq_data irq_data[MT6797_IRQ_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [MT6797_IRQ_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .id = MT6797_IRQ_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .irq_cnt_shift = AFE_IRQ_MCU_CNT1_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .irq_cnt_maskbit = AFE_IRQ_MCU_CNT1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .irq_fs_shift = IRQ1_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .irq_en_shift = IRQ1_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .irq_clr_shift = IRQ1_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) [MT6797_IRQ_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .id = MT6797_IRQ_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .irq_cnt_shift = AFE_IRQ_MCU_CNT2_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .irq_cnt_maskbit = AFE_IRQ_MCU_CNT2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .irq_fs_shift = IRQ2_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .irq_en_shift = IRQ2_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .irq_clr_shift = IRQ2_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) [MT6797_IRQ_3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .id = MT6797_IRQ_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .irq_cnt_shift = AFE_IRQ_MCU_CNT3_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .irq_cnt_maskbit = AFE_IRQ_MCU_CNT3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .irq_fs_shift = IRQ3_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .irq_en_shift = IRQ3_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .irq_clr_shift = IRQ3_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [MT6797_IRQ_4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .id = MT6797_IRQ_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .irq_cnt_shift = AFE_IRQ_MCU_CNT4_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .irq_cnt_maskbit = AFE_IRQ_MCU_CNT4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .irq_fs_shift = IRQ4_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .irq_en_shift = IRQ4_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .irq_clr_shift = IRQ4_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) [MT6797_IRQ_7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .id = MT6797_IRQ_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .irq_cnt_shift = AFE_IRQ_MCU_CNT7_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .irq_cnt_maskbit = AFE_IRQ_MCU_CNT7_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .irq_fs_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .irq_fs_shift = IRQ7_MCU_MODE_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .irq_en_reg = AFE_IRQ_MCU_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .irq_en_shift = IRQ7_MCU_ON_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .irq_clr_reg = AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .irq_clr_shift = IRQ7_MCU_CLR_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const struct regmap_config mt6797_afe_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .max_register = AFE_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static irqreturn_t mt6797_afe_irq_handler(int irq_id, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct mtk_base_afe *afe = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct mtk_base_afe_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned int mcu_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) irqreturn_t irq_ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* get irq that is sent to MCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (ret || (status & mcu_en) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __func__, ret, status, mcu_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* only clear IRQ which is sent to MCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) status = mcu_en & AFE_IRQ_STATUS_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) irq_ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) for (i = 0; i < MT6797_MEMIF_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct mtk_base_afe_memif *memif = &afe->memif[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!memif->substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) irq = &afe->irqs[memif->irq_usage];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (status & (1 << irq->irq_data->irq_en_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) snd_pcm_period_elapsed(memif->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* clear irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) regmap_write(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) AFE_IRQ_MCU_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) status & AFE_IRQ_STATUS_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return irq_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int mt6797_afe_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct mtk_base_afe *afe = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned int afe_on_retm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* disable AFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) regmap_read(afe->regmap, AFE_DAC_CON0, &afe_on_retm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if ((afe_on_retm & AFE_ON_RETM_MASK_SFT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) } while (++retry < 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_warn(afe->dev, "%s(), retry %d\n", __func__, retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* make sure all irq status are cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return mt6797_afe_disable_clock(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int mt6797_afe_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct mtk_base_afe *afe = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ret = mt6797_afe_enable_clock(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* irq signal to mcu only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) regmap_write(afe->regmap, AFE_IRQ_MCU_EN, AFE_IRQ_MCU_EN_MASK_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* force all memif use normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) regmap_update_bits(afe->regmap, AFE_MEMIF_HDALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 0x7ff << 16, 0x7ff << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* force cpu use normal mode when access sram data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) CPU_COMPACT_MODE_MASK_SFT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* force cpu use 8_24 format when writing 32bit data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) CPU_HD_ALIGN_MASK_SFT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* set all output port to 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 0x3fffffff, 0x3fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* enable AFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) regmap_update_bits(afe->regmap, AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) AFE_ON_MASK_SFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 0x1 << AFE_ON_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int mt6797_afe_component_probe(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return mtk_afe_add_sub_dai_control(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const struct snd_soc_component_driver mt6797_afe_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .name = AFE_PCM_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .probe = mt6797_afe_component_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .pointer = mtk_afe_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .pcm_construct = mtk_afe_pcm_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int mt6797_dai_memif_register(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct mtk_base_afe_dai *dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) list_add(&dai->list, &afe->sub_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dai->dai_drivers = mt6797_memif_dai_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dai->num_dai_drivers = ARRAY_SIZE(mt6797_memif_dai_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dai->dapm_widgets = mt6797_memif_widgets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dai->num_dapm_widgets = ARRAY_SIZE(mt6797_memif_widgets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dai->dapm_routes = mt6797_memif_routes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dai->num_dapm_routes = ARRAY_SIZE(mt6797_memif_routes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) typedef int (*dai_register_cb)(struct mtk_base_afe *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const dai_register_cb dai_register_cbs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mt6797_dai_adda_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mt6797_dai_pcm_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mt6797_dai_hostless_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) mt6797_dai_memif_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int mt6797_afe_pcm_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct mtk_base_afe *afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct mt6797_afe_private *afe_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int i, irq_id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!afe->platform_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) afe->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev = afe->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* initial audio related clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = mt6797_init_clock(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_err(dev, "init clock error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* regmap init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (IS_ERR(afe->base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return PTR_ERR(afe->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) &mt6797_afe_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (IS_ERR(afe->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return PTR_ERR(afe->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* init memif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) afe->memif_size = MT6797_MEMIF_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!afe->memif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) for (i = 0; i < afe->memif_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) afe->memif[i].data = &memif_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) afe->memif[i].irq_usage = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mutex_init(&afe->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* irq initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) afe->irqs_size = MT6797_IRQ_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (!afe->irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) for (i = 0; i < afe->irqs_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) afe->irqs[i].irq_data = &irq_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* request irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) irq_id = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (irq_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return irq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = devm_request_irq(dev, irq_id, mt6797_afe_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_err(dev, "could not request_irq for asys-isr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* init sub_dais */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) INIT_LIST_HEAD(&afe->sub_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = dai_register_cbs[i](afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* init dai_driver and component_driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = mtk_afe_combine_sub_dai(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) afe->mtk_afe_hardware = &mt6797_afe_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) afe->memif_fs = mt6797_memif_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) afe->irq_fs = mt6797_irq_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) afe->runtime_resume = mt6797_afe_runtime_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) afe->runtime_suspend = mt6797_afe_runtime_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) platform_set_drvdata(pdev, afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!pm_runtime_enabled(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* register component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = devm_snd_soc_register_component(dev, &mt6797_afe_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_warn(dev, "err_platform\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ret = devm_snd_soc_register_component(afe->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) &mt6797_afe_pcm_dai_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) afe->dai_drivers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) afe->num_dai_drivers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_warn(dev, "err_dai_component\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int mt6797_afe_pcm_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) mt6797_afe_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const struct of_device_id mt6797_afe_pcm_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) { .compatible = "mediatek,mt6797-audio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MODULE_DEVICE_TABLE(of, mt6797_afe_pcm_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static const struct dev_pm_ops mt6797_afe_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) SET_RUNTIME_PM_OPS(mt6797_afe_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) mt6797_afe_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static struct platform_driver mt6797_afe_pcm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "mt6797-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .of_match_table = mt6797_afe_pcm_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .pm = &mt6797_afe_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .probe = mt6797_afe_pcm_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .remove = mt6797_afe_pcm_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) module_platform_driver(mt6797_afe_pcm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 6797");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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