^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // mt6797-afe-clk.c -- Mediatek 6797 afe clock ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "mt6797-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "mt6797-afe-clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) CLK_INFRA_SYS_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) CLK_INFRA_SYS_AUD_26M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) CLK_TOP_MUX_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) CLK_TOP_MUX_AUD_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) CLK_TOP_SYSPLL3_D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) CLK_TOP_SYSPLL1_D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) CLK_CLK26M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) CLK_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const char *aud_clks[CLK_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [CLK_INFRA_SYS_AUD] = "infra_sys_audio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [CLK_INFRA_SYS_AUD_26M] = "infra_sys_audio_26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) [CLK_TOP_MUX_AUD] = "top_mux_audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [CLK_TOP_MUX_AUD_BUS] = "top_mux_aud_intbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [CLK_TOP_SYSPLL3_D4] = "top_sys_pll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [CLK_TOP_SYSPLL1_D4] = "top_sys_pll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [CLK_CLK26M] = "top_clk26m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int mt6797_init_clock(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct mt6797_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (!afe_priv->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) for (i = 0; i < CLK_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (IS_ERR(afe_priv->clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __func__, aud_clks[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PTR_ERR(afe_priv->clk[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return PTR_ERR(afe_priv->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int mt6797_afe_enable_clock(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct mt6797_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __func__, aud_clks[CLK_INFRA_SYS_AUD], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) goto CLK_INFRA_SYS_AUDIO_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __func__, aud_clks[CLK_INFRA_SYS_AUD_26M], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) goto CLK_INFRA_SYS_AUD_26M_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __func__, aud_clks[CLK_TOP_MUX_AUD], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) goto CLK_MUX_AUDIO_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) afe_priv->clk[CLK_CLK26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __func__, aud_clks[CLK_TOP_MUX_AUD],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) aud_clks[CLK_CLK26M], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto CLK_MUX_AUDIO_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __func__, aud_clks[CLK_TOP_MUX_AUD_BUS], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) goto CLK_MUX_AUDIO_INTBUS_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) CLK_MUX_AUDIO_INTBUS_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CLK_MUX_AUDIO_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CLK_INFRA_SYS_AUD_26M_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CLK_INFRA_SYS_AUDIO_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int mt6797_afe_disable_clock(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct mt6797_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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