^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mt2701-reg.h -- Mediatek 2701 audio driver reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Garlic Tseng <garlic.tseng@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _MT2701_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _MT2701_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AUDIO_TOP_CON0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AUDIO_TOP_CON4 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AUDIO_TOP_CON5 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AFE_DAIBT_CON0 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AFE_MRGIF_CON 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ASMI_TIMING_CON1 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ASMO_TIMING_CON1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PWR1_ASM_CON1 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ASYS_TOP_CON 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ASYS_I2SIN1_CON 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ASYS_I2SIN2_CON 0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ASYS_I2SIN3_CON 0x060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ASYS_I2SIN4_CON 0x0610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ASYS_I2SIN5_CON 0x0614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ASYS_I2SO1_CON 0x061C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ASYS_I2SO2_CON 0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ASYS_I2SO3_CON 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ASYS_I2SO4_CON 0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ASYS_I2SO5_CON 0x062c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PWR2_TOP_CON 0x0634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AFE_CONN0 0x06c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AFE_CONN1 0x06c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AFE_CONN2 0x06c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AFE_CONN3 0x06cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AFE_CONN14 0x06f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AFE_CONN15 0x06fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AFE_CONN16 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AFE_CONN17 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AFE_CONN18 0x0708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AFE_CONN19 0x070c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AFE_CONN20 0x0710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AFE_CONN21 0x0714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AFE_CONN22 0x0718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AFE_CONN23 0x071c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AFE_CONN24 0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AFE_CONN41 0x0764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ASYS_IRQ1_CON 0x0780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ASYS_IRQ2_CON 0x0784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ASYS_IRQ3_CON 0x0788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ASYS_IRQ_CLR 0x07c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ASYS_IRQ_STATUS 0x07c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PWR2_ASM_CON1 0x1070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AFE_DAC_CON0 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AFE_DAC_CON1 0x1204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AFE_DAC_CON2 0x1208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AFE_DAC_CON3 0x120c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AFE_DAC_CON4 0x1210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AFE_MEMIF_HD_CON1 0x121c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AFE_MEMIF_PBUF_SIZE 0x1238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AFE_MEMIF_HD_CON0 0x123c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AFE_DL1_BASE 0x1240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AFE_DL1_CUR 0x1244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AFE_DL2_BASE 0x1250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AFE_DL2_CUR 0x1254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AFE_DL3_BASE 0x1260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AFE_DL3_CUR 0x1264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AFE_DL4_BASE 0x1270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AFE_DL4_CUR 0x1274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AFE_DL5_BASE 0x1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AFE_DL5_CUR 0x1284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AFE_DLMCH_BASE 0x12a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AFE_DLMCH_CUR 0x12a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AFE_ARB1_BASE 0x12b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AFE_ARB1_CUR 0x12b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AFE_VUL_BASE 0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AFE_VUL_CUR 0x130c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AFE_UL2_BASE 0x1310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AFE_UL2_END 0x1318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AFE_UL2_CUR 0x131c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AFE_UL3_BASE 0x1320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AFE_UL3_END 0x1328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AFE_UL3_CUR 0x132c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AFE_UL4_BASE 0x1330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AFE_UL4_END 0x1338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AFE_UL4_CUR 0x133c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AFE_UL5_BASE 0x1340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AFE_UL5_END 0x1348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AFE_UL5_CUR 0x134c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AFE_DAI_BASE 0x1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AFE_DAI_CUR 0x137c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* AFE_DAIBT_CON0 (0x001c) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AFE_DAIBT_CON0_MRG_USE (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* PWR1_ASM_CON1 (0x0108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PWR1_ASM_CON1_INIT_VAL (0x492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* AFE_MRGIF_CON (0x003c) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AFE_MRGIF_CON_MRG_EN (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* ASYS_TOP_CON (0x0600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* PWR2_ASM_CON1 (0x1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PWR2_ASM_CON1_INIT_VAL (0x492492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* AFE_DAC_CON0 (0x1200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AFE_DAC_CON0_AFE_ON (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* AFE_MEMIF_PBUF_SIZE (0x1238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE (0x0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DLMCH_BIT_WIDTH_MASK (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AFE_MEMIF_PBUF_SIZE_DLM_CH(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* I2S in/out register bit control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ASYS_I2S_CON_FS (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ASYS_I2S_CON_FS_SET(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ASYS_I2S_CON_RESET (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ASYS_I2S_CON_I2S_EN (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ASYS_I2S_CON_ONE_HEART_MODE (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ASYS_I2S_CON_I2S_COUPLE_MODE (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 0:EIAJ 1:I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ASYS_I2S_CON_I2S_MODE (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ASYS_I2S_CON_WIDE_MODE (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ASYS_I2S_IN_PHASE_FIX (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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