Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * mt2701-cs42448.c  --  MT2701 CS42448 ALSA SoC machine driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Ir Lian <ir.lian@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	   Garlic Tseng <garlic.tseng@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "mt2701-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct mt2701_cs42448_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	int i2s1_in_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	int i2s1_in_mux_gpio_sel_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	int i2s1_in_mux_gpio_sel_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static const char * const i2sin_mux_switch_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	"ADC_SDOUT2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	"ADC_SDOUT3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	"I2S_IN_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	"I2S_IN_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static const struct soc_enum i2sin_mux_enum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	SOC_ENUM_SINGLE_EXT(4, i2sin_mux_switch_text);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static int mt2701_cs42448_i2sin1_mux_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 					 struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	ucontrol->value.integer.value[0] = priv->i2s1_in_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int mt2701_cs42448_i2sin1_mux_set(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 					 struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (ucontrol->value.integer.value[0] == priv->i2s1_in_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	switch (ucontrol->value.integer.value[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		dev_warn(card->dev, "%s invalid setting\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	priv->i2s1_in_mux = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static const struct snd_soc_dapm_widget
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			mt2701_cs42448_asoc_card_dapm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	SND_SOC_DAPM_LINE("Line Out Jack", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	SND_SOC_DAPM_MIC("AMIC", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	SND_SOC_DAPM_LINE("Tuner In", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	SND_SOC_DAPM_LINE("Satellite Tuner In", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	SND_SOC_DAPM_LINE("AUX In", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static const struct snd_kcontrol_new mt2701_cs42448_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	SOC_DAPM_PIN_SWITCH("Line Out Jack"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	SOC_DAPM_PIN_SWITCH("AMIC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	SOC_DAPM_PIN_SWITCH("Tuner In"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	SOC_DAPM_PIN_SWITCH("Satellite Tuner In"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	SOC_DAPM_PIN_SWITCH("AUX In"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	SOC_ENUM_EXT("I2SIN1_MUX_Switch", i2sin_mux_enum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		     mt2701_cs42448_i2sin1_mux_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		     mt2701_cs42448_i2sin1_mux_set),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static const unsigned int mt2701_cs42448_sampling_rates[] = {48000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct snd_pcm_hw_constraint_list mt2701_cs42448_constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.count = ARRAY_SIZE(mt2701_cs42448_sampling_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.list = mt2701_cs42448_sampling_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int mt2701_cs42448_fe_ops_startup(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	err = snd_pcm_hw_constraint_list(substream->runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 					 SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					 &mt2701_cs42448_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		dev_err(substream->pcm->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			"%s snd_pcm_hw_constraint_list failed: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			__func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct snd_soc_ops mt2701_cs42448_48k_fe_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.startup = mt2701_cs42448_fe_ops_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int mt2701_cs42448_be_ops_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 					   struct snd_pcm_hw_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	unsigned int mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	unsigned int rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	unsigned int div_mclk_over_bck = rate > 192000 ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned int div_bck_over_lrck = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mclk_rate = rate * div_bck_over_lrck * div_mclk_over_bck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* mt2701 mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, SND_SOC_CLOCK_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* codec mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, SND_SOC_CLOCK_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct snd_soc_ops mt2701_cs42448_be_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.hw_params = mt2701_cs42448_be_ops_hw_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	DAI_LINK_FE_MULTI_CH_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	DAI_LINK_FE_PCM0_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	DAI_LINK_FE_PCM1_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	DAI_LINK_FE_BT_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	DAI_LINK_FE_BT_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	DAI_LINK_BE_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	DAI_LINK_BE_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	DAI_LINK_BE_I2S2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	DAI_LINK_BE_I2S3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	DAI_LINK_BE_MRG_BT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SND_SOC_DAILINK_DEFS(fe_multi_ch_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	DAILINK_COMP_ARRAY(COMP_CPU("PCM_multi")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	DAILINK_COMP_ARRAY(COMP_DUMMY()),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SND_SOC_DAILINK_DEFS(fe_pcm0_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	DAILINK_COMP_ARRAY(COMP_CPU("PCM0")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	DAILINK_COMP_ARRAY(COMP_DUMMY()),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SND_SOC_DAILINK_DEFS(fe_pcm1_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	DAILINK_COMP_ARRAY(COMP_CPU("PCM1")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	DAILINK_COMP_ARRAY(COMP_DUMMY()),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SND_SOC_DAILINK_DEFS(fe_bt_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	DAILINK_COMP_ARRAY(COMP_CPU("PCM_BT_DL")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	DAILINK_COMP_ARRAY(COMP_DUMMY()),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SND_SOC_DAILINK_DEFS(fe_bt_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	DAILINK_COMP_ARRAY(COMP_CPU("PCM_BT_UL")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	DAILINK_COMP_ARRAY(COMP_DUMMY()),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SND_SOC_DAILINK_DEFS(be_i2s0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SND_SOC_DAILINK_DEFS(be_i2s1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SND_SOC_DAILINK_DEFS(be_i2s2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SND_SOC_DAILINK_DEFS(be_i2s3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SND_SOC_DAILINK_DEFS(be_mrg_bt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	DAILINK_COMP_ARRAY(COMP_CPU("MRG BT")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "bt-sco-pcm-wb")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	DAILINK_COMP_ARRAY(COMP_EMPTY()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct snd_soc_dai_link mt2701_cs42448_dai_links[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	[DAI_LINK_FE_MULTI_CH_OUT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.name = "mt2701-cs42448-multi-ch-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.stream_name = "mt2701-cs42448-multi-ch-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			    SND_SOC_DPCM_TRIGGER_POST},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.ops = &mt2701_cs42448_48k_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.dynamic = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.dpcm_playback = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		SND_SOC_DAILINK_REG(fe_multi_ch_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	[DAI_LINK_FE_PCM0_IN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.name = "mt2701-cs42448-pcm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.stream_name = "mt2701-cs42448-pcm0-data-UL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			    SND_SOC_DPCM_TRIGGER_POST},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.ops = &mt2701_cs42448_48k_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.dynamic = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.dpcm_capture = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		SND_SOC_DAILINK_REG(fe_pcm0_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	[DAI_LINK_FE_PCM1_IN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.name = "mt2701-cs42448-pcm1-data-UL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.stream_name = "mt2701-cs42448-pcm1-data-UL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			    SND_SOC_DPCM_TRIGGER_POST},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.ops = &mt2701_cs42448_48k_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.dynamic = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		.dpcm_capture = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		SND_SOC_DAILINK_REG(fe_pcm1_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	[DAI_LINK_FE_BT_OUT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.name = "mt2701-cs42448-pcm-BT-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.stream_name = "mt2701-cs42448-pcm-BT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			    SND_SOC_DPCM_TRIGGER_POST},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.dynamic = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.dpcm_playback = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		SND_SOC_DAILINK_REG(fe_bt_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	[DAI_LINK_FE_BT_IN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.name = "mt2701-cs42448-pcm-BT-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.stream_name = "mt2701-cs42448-pcm-BT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			    SND_SOC_DPCM_TRIGGER_POST},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.dynamic = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.dpcm_capture = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		SND_SOC_DAILINK_REG(fe_bt_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	[DAI_LINK_BE_I2S0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.name = "mt2701-cs42448-I2S0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.no_pcm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			 | SND_SOC_DAIFMT_GATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.ops = &mt2701_cs42448_be_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.dpcm_playback = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.dpcm_capture = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		SND_SOC_DAILINK_REG(be_i2s0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	[DAI_LINK_BE_I2S1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.name = "mt2701-cs42448-I2S1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.no_pcm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			 | SND_SOC_DAIFMT_GATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.ops = &mt2701_cs42448_be_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.dpcm_playback = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.dpcm_capture = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		SND_SOC_DAILINK_REG(be_i2s1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	[DAI_LINK_BE_I2S2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.name = "mt2701-cs42448-I2S2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.no_pcm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			 | SND_SOC_DAIFMT_GATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.ops = &mt2701_cs42448_be_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.dpcm_playback = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.dpcm_capture = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		SND_SOC_DAILINK_REG(be_i2s2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	[DAI_LINK_BE_I2S3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.name = "mt2701-cs42448-I2S3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.no_pcm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			 | SND_SOC_DAIFMT_GATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.ops = &mt2701_cs42448_be_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.dpcm_playback = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.dpcm_capture = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		SND_SOC_DAILINK_REG(be_i2s3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	[DAI_LINK_BE_MRG_BT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.name = "mt2701-cs42448-MRG-BT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.no_pcm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.dpcm_playback = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.dpcm_capture = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		SND_SOC_DAILINK_REG(be_mrg_bt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct snd_soc_card mt2701_cs42448_soc_card = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.name = "mt2701-cs42448",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.dai_link = mt2701_cs42448_dai_links,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.num_links = ARRAY_SIZE(mt2701_cs42448_dai_links),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.controls = mt2701_cs42448_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.num_controls = ARRAY_SIZE(mt2701_cs42448_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.dapm_widgets = mt2701_cs42448_asoc_card_dapm_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.num_dapm_widgets = ARRAY_SIZE(mt2701_cs42448_asoc_card_dapm_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int mt2701_cs42448_machine_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct snd_soc_card *card = &mt2701_cs42448_soc_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	struct device_node *platform_node, *codec_node, *codec_node_bt_mrg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	struct mt2701_cs42448_private *priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		devm_kzalloc(&pdev->dev, sizeof(struct mt2701_cs42448_private),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct snd_soc_dai_link *dai_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	platform_node = of_parse_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 					 "mediatek,platform", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (!platform_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	for_each_card_prelinks(card, i, dai_link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		if (dai_link->platforms->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		dai_link->platforms->of_node = platform_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	card->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	codec_node = of_parse_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				      "mediatek,audio-codec", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (!codec_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			"Property 'audio-codec' missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	for_each_card_prelinks(card, i, dai_link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (dai_link->codecs->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		dai_link->codecs->of_node = codec_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	codec_node_bt_mrg = of_parse_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 					     "mediatek,audio-codec-bt-mrg", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (!codec_node_bt_mrg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			"Property 'audio-codec-bt-mrg' missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	mt2701_cs42448_dai_links[DAI_LINK_BE_MRG_BT].codecs->of_node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 							= codec_node_bt_mrg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	priv->i2s1_in_mux_gpio_sel_1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio1", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 					"i2s1_in_mux_gpio_sel_1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			dev_warn(&pdev->dev, "%s devm_gpio_request fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 				 __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		gpio_direction_output(priv->i2s1_in_mux_gpio_sel_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	priv->i2s1_in_mux_gpio_sel_2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio2", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 					"i2s1_in_mux_gpio_sel_2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			dev_warn(&pdev->dev, "%s devm_gpio_request fail2 %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 				 __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		gpio_direction_output(priv->i2s1_in_mux_gpio_sel_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	snd_soc_card_set_drvdata(card, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	ret = devm_snd_soc_register_card(&pdev->dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			__func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct of_device_id mt2701_cs42448_machine_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	{.compatible = "mediatek,mt2701-cs42448-machine",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct platform_driver mt2701_cs42448_machine = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		.name = "mt2701-cs42448",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		   #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		   .of_match_table = mt2701_cs42448_machine_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		   #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.probe = mt2701_cs42448_machine_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) module_platform_driver(mt2701_cs42448_machine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MODULE_DESCRIPTION("MT2701 CS42448 ALSA SoC machine driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MODULE_AUTHOR("Ir Lian <ir.lian@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_ALIAS("mt2701 cs42448 soc card");