^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Mediatek ALSA SoC AFE platform driver for 2701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Garlic Tseng <garlic.tseng@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Ir Lian <ir.lian@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "mt2701-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "mt2701-afe-clock-ctrl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../common/mtk-afe-platform-driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "../common/mtk-afe-fe-dai.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct snd_pcm_hardware mt2701_afe_hardware = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .period_bytes_min = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .period_bytes_max = 1024 * 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .periods_min = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .buffer_bytes_max = 1024 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct mt2701_afe_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int regvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct mt2701_afe_rate mt2701_afe_i2s_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { .rate = 8000, .regvalue = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { .rate = 12000, .regvalue = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .rate = 16000, .regvalue = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .rate = 24000, .regvalue = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .rate = 32000, .regvalue = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { .rate = 48000, .regvalue = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { .rate = 96000, .regvalue = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { .rate = 192000, .regvalue = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .rate = 384000, .regvalue = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .rate = 7350, .regvalue = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .rate = 11025, .regvalue = 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { .rate = 14700, .regvalue = 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .rate = 22050, .regvalue = 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .rate = 29400, .regvalue = 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .rate = 44100, .regvalue = 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .rate = 88200, .regvalue = 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .rate = 176400, .regvalue = 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .rate = 352800, .regvalue = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const unsigned int mt2701_afe_backup_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) AUDIO_TOP_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) AUDIO_TOP_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ASYS_TOP_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) AFE_CONN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) AFE_CONN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) AFE_CONN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) AFE_CONN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) AFE_CONN15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) AFE_CONN16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) AFE_CONN17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) AFE_CONN18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) AFE_CONN19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) AFE_CONN20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) AFE_CONN21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) AFE_CONN22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) AFE_MEMIF_PBUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int mt2701_dai_num_to_i2s(struct mtk_base_afe *afe, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int val = num - MT2701_IO_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (val < 0 || val >= afe_priv->soc->i2s_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_err(afe->dev, "%s, num not available, num %d, val %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __func__, num, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int mt2701_afe_i2s_fs(unsigned int sample_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) for (i = 0; i < ARRAY_SIZE(mt2701_afe_i2s_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (mt2701_afe_i2s_rates[i].rate == sample_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return mt2701_afe_i2s_rates[i].regvalue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bool mode = afe_priv->soc->has_one_heart_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (i2s_num < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return i2s_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return mt2701_afe_enable_mclk(afe, mode ? 1 : i2s_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int mt2701_afe_i2s_path_disable(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct mt2701_i2s_path *i2s_path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int stream_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (--i2s_path->on[stream_dir] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) i2s_path->on[stream_dir] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (i2s_path->on[stream_dir])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* disable i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ASYS_I2S_CON_I2S_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mt2701_afe_disable_i2s(afe, i2s_path, stream_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct mt2701_i2s_path *i2s_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool mode = afe_priv->soc->has_one_heart_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (i2s_num < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) i2s_path = &afe_priv->i2s_path[i2s_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (i2s_path->occupied[substream->stream])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) i2s_path->occupied[substream->stream] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mt2701_afe_i2s_path_disable(afe, i2s_path, substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* need to disable i2s-out path when disable i2s-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mt2701_afe_i2s_path_disable(afe, i2s_path, !substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* disable mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mt2701_afe_disable_mclk(afe, mode ? 1 : i2s_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int mt2701_i2s_path_enable(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct mt2701_i2s_path *i2s_path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int stream_dir, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int reg, fs, w_len = 1; /* now we support bck 64bits only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* no need to enable if already done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (++i2s_path->on[stream_dir] != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) fs = mt2701_afe_i2s_fs(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mask = ASYS_I2S_CON_FS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ASYS_I2S_CON_I2S_COUPLE_MODE | /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ASYS_I2S_CON_I2S_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ASYS_I2S_CON_WIDE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val = ASYS_I2S_CON_FS_SET(fs) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ASYS_I2S_CON_I2S_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ASYS_I2S_CON_WIDE_MODE_SET(w_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (stream_dir == SNDRV_PCM_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mask |= ASYS_I2S_IN_PHASE_FIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val |= ASYS_I2S_IN_PHASE_FIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg = ASMI_TIMING_CON1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (afe_priv->soc->has_one_heart_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mask |= ASYS_I2S_CON_ONE_HEART_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) val |= ASYS_I2S_CON_ONE_HEART_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) reg = ASMO_TIMING_CON1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) regmap_update_bits(afe->regmap, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) i2s_data->i2s_asrc_fs_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) << i2s_data->i2s_asrc_fs_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) fs << i2s_data->i2s_asrc_fs_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* enable i2s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mt2701_afe_enable_i2s(afe, i2s_path, stream_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* reset i2s hw status before enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ASYS_I2S_CON_RESET, ASYS_I2S_CON_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ASYS_I2S_CON_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ASYS_I2S_CON_I2S_EN, ASYS_I2S_CON_I2S_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int ret, i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct mt2701_i2s_path *i2s_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bool mode = afe_priv->soc->has_one_heart_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (i2s_num < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return i2s_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) i2s_path = &afe_priv->i2s_path[i2s_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (i2s_path->occupied[substream->stream])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = mt2701_mclk_configuration(afe, mode ? 1 : i2s_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) i2s_path->occupied[substream->stream] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* need to enable i2s-out path when enable i2s-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mt2701_i2s_path_enable(afe, i2s_path, !substream->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) substream->runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mt2701_i2s_path_enable(afe, i2s_path, substream->stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) substream->runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int freq, int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) bool mode = afe_priv->soc->has_one_heart_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (i2s_num < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return i2s_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (dir == SND_SOC_CLOCK_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_warn(dai->dev, "The SoCs doesn't support mclk input\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) afe_priv->i2s_path[mode ? 1 : i2s_num].mclk_rate = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = mt2701_enable_btmrg_clk(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) afe_priv->mrg_enable[substream->stream] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int mt2701_btmrg_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int stream_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 val, msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) stream_fs = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (stream_fs != 8000 && stream_fs != 16000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(afe->dev, "unsupported rate %d\n", stream_fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) AFE_MRGIF_CON_I2S_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) AFE_MRGIF_CON_I2S_MODE_32K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) | AFE_DAIBT_CON0_MRG_USE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) msk = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (stream_fs == 16000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) msk |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) AFE_DAIBT_CON0_DAIBT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) AFE_DAIBT_CON0_DAIBT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) AFE_MRGIF_CON_MRG_I2S_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) AFE_MRGIF_CON_MRG_I2S_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) AFE_MRGIF_CON_MRG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) AFE_MRGIF_CON_MRG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* if the other direction stream is not occupied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!afe_priv->mrg_enable[!substream->stream]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) AFE_DAIBT_CON0_DAIBT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) AFE_MRGIF_CON_MRG_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) AFE_MRGIF_CON_MRG_I2S_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mt2701_disable_btmrg_clk(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) afe_priv->mrg_enable[substream->stream] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int mt2701_simple_fe_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct mtk_base_afe_memif *memif_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int stream_dir = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* can't run single DL & DLM at the same time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) memif_tmp = &afe->memif[MT2701_MEMIF_DLM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (memif_tmp->substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_warn(afe->dev, "memif is not available");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return mtk_afe_fe_startup(substream, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int mt2701_simple_fe_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int stream_dir = substream->stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* single DL use PAIR_INTERLEAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) AFE_MEMIF_PBUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) AFE_MEMIF_PBUF_SIZE_DLM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return mtk_afe_fe_hw_params(substream, params, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int mt2701_dlm_fe_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct mtk_base_afe_memif *memif_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) const struct mtk_base_memif_data *memif_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) memif_tmp = &afe->memif[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (memif_tmp->substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* enable agent for all signal DL (due to hw design) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) memif_data = afe->memif[i].data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) memif_data->agent_disable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 1 << memif_data->agent_disable_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0 << memif_data->agent_disable_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return mtk_afe_fe_startup(substream, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) const struct mtk_base_memif_data *memif_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) memif_data = afe->memif[i].data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) memif_data->agent_disable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 1 << memif_data->agent_disable_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 1 << memif_data->agent_disable_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return mtk_afe_fe_shutdown(substream, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int channels = params_channels(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) AFE_MEMIF_PBUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) AFE_MEMIF_PBUF_SIZE_DLM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) AFE_MEMIF_PBUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) AFE_MEMIF_PBUF_SIZE_DLM_32BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) regmap_update_bits(afe->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) AFE_MEMIF_PBUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) AFE_MEMIF_PBUF_SIZE_DLM_CH(channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return mtk_afe_fe_hw_params(substream, params, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int mt2701_dlm_fe_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int cmd, struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct mtk_base_afe_memif *memif_tmp = &afe->memif[MT2701_MEMIF_DL1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 1 << memif_tmp->data->enable_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 1 << memif_tmp->data->enable_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mtk_afe_fe_trigger(substream, cmd, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mtk_afe_fe_trigger(substream, cmd, dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 1 << memif_tmp->data->enable_shift, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int mt2701_memif_fs(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (asoc_rtd_to_cpu(rtd, 0)->id != MT2701_MEMIF_ULBT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) fs = mt2701_afe_i2s_fs(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) fs = (rate == 16000 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int mt2701_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return mt2701_afe_i2s_fs(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* FE DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .startup = mt2701_simple_fe_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .shutdown = mtk_afe_fe_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .hw_params = mt2701_simple_fe_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .hw_free = mtk_afe_fe_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .prepare = mtk_afe_fe_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .trigger = mtk_afe_fe_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .startup = mt2701_dlm_fe_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .shutdown = mt2701_dlm_fe_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .hw_params = mt2701_dlm_fe_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .hw_free = mtk_afe_fe_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .prepare = mtk_afe_fe_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .trigger = mt2701_dlm_fe_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* I2S BE DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const struct snd_soc_dai_ops mt2701_afe_i2s_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .startup = mt2701_afe_i2s_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .shutdown = mt2701_afe_i2s_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .prepare = mt2701_afe_i2s_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .set_sysclk = mt2701_afe_i2s_set_sysclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* MRG BE DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct snd_soc_dai_ops mt2701_btmrg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .startup = mt2701_btmrg_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .shutdown = mt2701_btmrg_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .hw_params = mt2701_btmrg_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* FE DAIs: memory intefaces to CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .name = "PCMO0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .id = MT2701_MEMIF_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .stream_name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .ops = &mt2701_single_memif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .name = "PCM_multi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .id = MT2701_MEMIF_DLM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .stream_name = "DLM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .channels_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ops = &mt2701_dlm_memif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .name = "PCM0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .id = MT2701_MEMIF_UL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .stream_name = "UL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .rates = SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .ops = &mt2701_single_memif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .name = "PCM1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .id = MT2701_MEMIF_UL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .stream_name = "UL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .ops = &mt2701_single_memif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = "PCM_BT_DL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .id = MT2701_MEMIF_DLBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .stream_name = "DLBT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .rates = (SNDRV_PCM_RATE_8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) | SNDRV_PCM_RATE_16000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .ops = &mt2701_single_memif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .name = "PCM_BT_UL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .id = MT2701_MEMIF_ULBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .stream_name = "ULBT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .rates = (SNDRV_PCM_RATE_8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) | SNDRV_PCM_RATE_16000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .ops = &mt2701_single_memif_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* BE DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .name = "I2S0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .id = MT2701_IO_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .stream_name = "I2S0 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .stream_name = "I2S0 Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .ops = &mt2701_afe_i2s_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .name = "I2S1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .id = MT2701_IO_2ND_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .stream_name = "I2S1 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .stream_name = "I2S1 Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .ops = &mt2701_afe_i2s_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .name = "I2S2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .id = MT2701_IO_3RD_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .stream_name = "I2S2 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .stream_name = "I2S2 Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .ops = &mt2701_afe_i2s_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .name = "I2S3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .id = MT2701_IO_4TH_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .stream_name = "I2S3 Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .stream_name = "I2S3 Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .rates = SNDRV_PCM_RATE_8000_192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .formats = (SNDRV_PCM_FMTBIT_S16_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) | SNDRV_PCM_FMTBIT_S24_LE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) | SNDRV_PCM_FMTBIT_S32_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .ops = &mt2701_afe_i2s_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .name = "MRG BT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .id = MT2701_IO_MRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .stream_name = "BT Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .rates = (SNDRV_PCM_RATE_8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) | SNDRV_PCM_RATE_16000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .stream_name = "BT Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .rates = (SNDRV_PCM_RATE_8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) | SNDRV_PCM_RATE_16000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .ops = &mt2701_btmrg_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .symmetric_rates = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const struct snd_kcontrol_new mt2701_afe_o00_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0, 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const struct snd_kcontrol_new mt2701_afe_o01_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const struct snd_kcontrol_new mt2701_afe_o02_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const struct snd_kcontrol_new mt2701_afe_o03_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 3, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct snd_kcontrol_new mt2701_afe_o14_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14, 26, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const struct snd_kcontrol_new mt2701_afe_o15_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15, 12, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const struct snd_kcontrol_new mt2701_afe_o16_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16, 13, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const struct snd_kcontrol_new mt2701_afe_o17_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct snd_kcontrol_new mt2701_afe_o18_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const struct snd_kcontrol_new mt2701_afe_o19_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const struct snd_kcontrol_new mt2701_afe_o20_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const struct snd_kcontrol_new mt2701_afe_o21_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const struct snd_kcontrol_new mt2701_afe_o22_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static const struct snd_kcontrol_new mt2701_afe_o31_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41, 9, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const struct snd_kcontrol_new mt2701_afe_i02_mix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM, 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ASYS_I2SO1_CON, 26, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ASYS_I2SO2_CON, 26, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PWR2_TOP_CON, 17, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PWR2_TOP_CON, 18, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* inter-connections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM, 0, 0, mt2701_afe_i02_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ARRAY_SIZE(mt2701_afe_i02_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM, 0, 0, NULL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, mt2701_afe_o00_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ARRAY_SIZE(mt2701_afe_o00_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, mt2701_afe_o01_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ARRAY_SIZE(mt2701_afe_o01_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM, 0, 0, mt2701_afe_o02_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ARRAY_SIZE(mt2701_afe_o02_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, mt2701_afe_o03_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ARRAY_SIZE(mt2701_afe_o03_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, mt2701_afe_o14_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ARRAY_SIZE(mt2701_afe_o14_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, mt2701_afe_o15_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ARRAY_SIZE(mt2701_afe_o15_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, mt2701_afe_o16_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ARRAY_SIZE(mt2701_afe_o16_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, mt2701_afe_o17_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ARRAY_SIZE(mt2701_afe_o17_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, mt2701_afe_o18_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ARRAY_SIZE(mt2701_afe_o18_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, mt2701_afe_o19_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ARRAY_SIZE(mt2701_afe_o19_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, mt2701_afe_o20_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ARRAY_SIZE(mt2701_afe_o20_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, mt2701_afe_o21_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ARRAY_SIZE(mt2701_afe_o21_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, mt2701_afe_o22_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ARRAY_SIZE(mt2701_afe_o22_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, mt2701_afe_o31_mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ARRAY_SIZE(mt2701_afe_o31_mix)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mt2701_afe_multi_ch_out_i2s0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) mt2701_afe_multi_ch_out_i2s1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) mt2701_afe_multi_ch_out_i2s2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) mt2701_afe_multi_ch_out_i2s3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {"I12", NULL, "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {"I13", NULL, "DL1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {"I35", NULL, "DLBT"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {"I2S0 Playback", NULL, "O15"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {"I2S0 Playback", NULL, "O16"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {"I2S1 Playback", NULL, "O17"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {"I2S1 Playback", NULL, "O18"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {"I2S2 Playback", NULL, "O19"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {"I2S2 Playback", NULL, "O20"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {"I2S3 Playback", NULL, "O21"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {"I2S3 Playback", NULL, "O22"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {"BT Playback", NULL, "O31"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {"UL1", NULL, "O00"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {"UL1", NULL, "O01"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {"UL2", NULL, "O02"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {"UL2", NULL, "O03"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {"ULBT", NULL, "O14"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {"I00", NULL, "I2S0 Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {"I01", NULL, "I2S0 Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {"I02", NULL, "I2S1 Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {"I03", NULL, "I2S1 Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* I02,03 link to UL2, also need to open I2S0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {"I02", "I2S0 Switch", "I2S0 Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {"I26", NULL, "BT Capture"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {"I12I13", "Multich I2S0 Out Switch", "DLM"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {"I14I15", "Multich I2S1 Out Switch", "DLM"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {"I16I17", "Multich I2S2 Out Switch", "DLM"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {"I18I19", "Multich I2S3 Out Switch", "DLM"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) { "I12", NULL, "I12I13" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) { "I13", NULL, "I12I13" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) { "I14", NULL, "I14I15" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) { "I15", NULL, "I14I15" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) { "I16", NULL, "I16I17" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { "I17", NULL, "I16I17" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { "I18", NULL, "I18I19" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) { "I19", NULL, "I18I19" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) { "O00", "I00 Switch", "I00" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) { "O01", "I01 Switch", "I01" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) { "O02", "I02 Switch", "I02" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) { "O03", "I03 Switch", "I03" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) { "O14", "I26 Switch", "I26" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { "O15", "I12 Switch", "I12" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { "O16", "I13 Switch", "I13" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) { "O17", "I14 Switch", "I14" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) { "O18", "I15 Switch", "I15" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) { "O19", "I16 Switch", "I16" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) { "O20", "I17 Switch", "I17" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { "O21", "I18 Switch", "I18" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { "O22", "I19 Switch", "I19" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { "O31", "I35 Switch", "I35" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int mt2701_afe_pcm_probe(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) snd_soc_component_init_regmap(component, afe->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .probe = mt2701_afe_pcm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .name = "mt2701-afe-pcm-dai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .dapm_widgets = mt2701_afe_pcm_widgets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .num_dapm_widgets = ARRAY_SIZE(mt2701_afe_pcm_widgets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .dapm_routes = mt2701_afe_pcm_routes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .num_dapm_routes = ARRAY_SIZE(mt2701_afe_pcm_routes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .suspend = mtk_afe_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .resume = mtk_afe_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .name = "DL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .id = MT2701_MEMIF_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .reg_ofs_base = AFE_DL1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .reg_ofs_cur = AFE_DL1_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .fs_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .mono_reg = AFE_DAC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .mono_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .enable_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .hd_reg = AFE_MEMIF_HD_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .hd_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .agent_disable_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .name = "DL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .id = MT2701_MEMIF_DL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .reg_ofs_base = AFE_DL2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .reg_ofs_cur = AFE_DL2_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .fs_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .mono_reg = AFE_DAC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .mono_shift = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .enable_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .hd_reg = AFE_MEMIF_HD_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .hd_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .agent_disable_shift = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .name = "DL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .id = MT2701_MEMIF_DL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .reg_ofs_base = AFE_DL3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .reg_ofs_cur = AFE_DL3_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .fs_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .mono_reg = AFE_DAC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .mono_shift = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .enable_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .hd_reg = AFE_MEMIF_HD_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .hd_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .agent_disable_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .name = "DL4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .id = MT2701_MEMIF_DL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .reg_ofs_base = AFE_DL4_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .reg_ofs_cur = AFE_DL4_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .fs_shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .mono_reg = AFE_DAC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .mono_shift = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .enable_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .hd_reg = AFE_MEMIF_HD_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .hd_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .agent_disable_shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .name = "DL5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .id = MT2701_MEMIF_DL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .reg_ofs_base = AFE_DL5_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .reg_ofs_cur = AFE_DL5_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .fs_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .mono_reg = AFE_DAC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .mono_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .enable_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .hd_reg = AFE_MEMIF_HD_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .hd_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .agent_disable_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .name = "DLM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .id = MT2701_MEMIF_DLM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .reg_ofs_base = AFE_DLMCH_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .reg_ofs_cur = AFE_DLMCH_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .fs_reg = AFE_DAC_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .fs_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .mono_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .mono_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .enable_shift = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .hd_reg = AFE_MEMIF_PBUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .hd_shift = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .agent_disable_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .name = "UL1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .id = MT2701_MEMIF_UL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .reg_ofs_base = AFE_VUL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .reg_ofs_cur = AFE_VUL_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .fs_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .fs_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .mono_reg = AFE_DAC_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .mono_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .enable_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .hd_reg = AFE_MEMIF_HD_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .hd_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .agent_disable_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .name = "UL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .id = MT2701_MEMIF_UL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .reg_ofs_base = AFE_UL2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .reg_ofs_cur = AFE_UL2_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .fs_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .fs_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .mono_reg = AFE_DAC_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .mono_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .enable_shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .hd_reg = AFE_MEMIF_HD_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .hd_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .agent_disable_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .name = "UL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .id = MT2701_MEMIF_UL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .reg_ofs_base = AFE_UL3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .reg_ofs_cur = AFE_UL3_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .fs_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .fs_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .mono_reg = AFE_DAC_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .mono_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .enable_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .hd_reg = AFE_MEMIF_HD_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .hd_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .agent_disable_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .name = "UL4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .id = MT2701_MEMIF_UL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .reg_ofs_base = AFE_UL4_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .reg_ofs_cur = AFE_UL4_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .fs_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .fs_shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .mono_reg = AFE_DAC_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .mono_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .enable_shift = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .hd_reg = AFE_MEMIF_HD_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .hd_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .agent_disable_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .name = "UL5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .id = MT2701_MEMIF_UL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .reg_ofs_base = AFE_UL5_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .reg_ofs_cur = AFE_UL5_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .fs_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .fs_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .mono_reg = AFE_DAC_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .mono_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .enable_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .hd_reg = AFE_MEMIF_HD_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .hd_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .agent_disable_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .name = "DLBT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .id = MT2701_MEMIF_DLBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .reg_ofs_base = AFE_ARB1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .reg_ofs_cur = AFE_ARB1_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .fs_reg = AFE_DAC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .fs_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .mono_reg = AFE_DAC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .mono_shift = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .enable_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .hd_reg = AFE_MEMIF_HD_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .hd_shift = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .agent_disable_shift = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .name = "ULBT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .id = MT2701_MEMIF_ULBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .reg_ofs_base = AFE_DAI_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .reg_ofs_cur = AFE_DAI_CUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .fs_reg = AFE_DAC_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .fs_shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .fs_maskbit = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .mono_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .mono_shift = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .enable_reg = AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .enable_shift = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .hd_reg = AFE_MEMIF_HD_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .hd_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .agent_disable_reg = AUDIO_TOP_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .agent_disable_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .msb_reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static const struct mtk_base_irq_data irq_data[MT2701_IRQ_ASYS_END] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .id = MT2701_IRQ_ASYS_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .irq_cnt_reg = ASYS_IRQ1_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .irq_cnt_maskbit = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .irq_fs_reg = ASYS_IRQ1_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .irq_fs_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .irq_fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .irq_en_reg = ASYS_IRQ1_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .irq_en_shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .irq_clr_reg = ASYS_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .irq_clr_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .id = MT2701_IRQ_ASYS_IRQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .irq_cnt_reg = ASYS_IRQ2_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .irq_cnt_maskbit = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .irq_fs_reg = ASYS_IRQ2_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .irq_fs_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .irq_fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .irq_en_reg = ASYS_IRQ2_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .irq_en_shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .irq_clr_reg = ASYS_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .irq_clr_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .id = MT2701_IRQ_ASYS_IRQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .irq_cnt_reg = ASYS_IRQ3_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .irq_cnt_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .irq_cnt_maskbit = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .irq_fs_reg = ASYS_IRQ3_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .irq_fs_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .irq_fs_maskbit = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .irq_en_reg = ASYS_IRQ3_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .irq_en_shift = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .irq_clr_reg = ASYS_IRQ_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .irq_clr_shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static const struct mt2701_i2s_data mt2701_i2s_data[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) { ASYS_I2SO1_CON, 0, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) { ASYS_I2SIN1_CON, 0, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) { ASYS_I2SO2_CON, 5, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) { ASYS_I2SIN2_CON, 5, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) { ASYS_I2SO3_CON, 10, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) { ASYS_I2SIN3_CON, 10, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) { ASYS_I2SO4_CON, 15, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) { ASYS_I2SIN4_CON, 15, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* TODO - extend control registers supported by newer SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct mtk_base_afe *afe = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct mtk_base_afe_memif *memif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct mtk_base_afe_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) regmap_read(afe->regmap, ASYS_IRQ_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) regmap_write(afe->regmap, ASYS_IRQ_CLR, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) for (id = 0; id < MT2701_MEMIF_NUM; ++id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) memif = &afe->memif[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (memif->irq_usage < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) irq = &afe->irqs[memif->irq_usage];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (status & 1 << irq->irq_data->irq_clr_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) snd_pcm_period_elapsed(memif->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static int mt2701_afe_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct mtk_base_afe *afe = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return mt2701_afe_disable_clock(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static int mt2701_afe_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct mtk_base_afe *afe = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return mt2701_afe_enable_clock(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct mtk_base_afe *afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct mt2701_afe_private *afe_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int i, irq_id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (!afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (!afe->platform_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) afe_priv->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) afe->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) dev = afe->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) afe_priv->i2s_path = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) afe_priv->soc->i2s_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) sizeof(struct mt2701_i2s_path),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (!afe_priv->i2s_path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) irq_id = platform_get_irq_byname(pdev, "asys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (irq_id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return irq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = devm_request_irq(dev, irq_id, mt2701_asys_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev_err(dev, "could not request_irq for asys-isr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (IS_ERR(afe->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_err(dev, "could not get regmap from parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return PTR_ERR(afe->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) mutex_init(&afe->irq_alloc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* memif initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) afe->memif_size = MT2701_MEMIF_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (!afe->memif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) for (i = 0; i < afe->memif_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) afe->memif[i].data = &memif_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) afe->memif[i].irq_usage = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* irq initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) afe->irqs_size = MT2701_IRQ_ASYS_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (!afe->irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) for (i = 0; i < afe->irqs_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) afe->irqs[i].irq_data = &irq_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* I2S initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) for (i = 0; i < afe_priv->soc->i2s_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_PLAYBACK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) &mt2701_i2s_data[i][SNDRV_PCM_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_CAPTURE] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) &mt2701_i2s_data[i][SNDRV_PCM_STREAM_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) afe->mtk_afe_hardware = &mt2701_afe_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) afe->memif_fs = mt2701_memif_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) afe->irq_fs = mt2701_irq_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) afe->reg_back_up_list = mt2701_afe_backup_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) afe->runtime_resume = mt2701_afe_runtime_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) afe->runtime_suspend = mt2701_afe_runtime_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* initial audio related clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = mt2701_init_clock(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) dev_err(dev, "init clock error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) platform_set_drvdata(pdev, afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (!pm_runtime_enabled(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ret = mt2701_afe_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ret = devm_snd_soc_register_component(&pdev->dev, &mtk_afe_pcm_platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_warn(dev, "err_platform\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) goto err_platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ret = devm_snd_soc_register_component(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) &mt2701_afe_pcm_dai_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) mt2701_afe_pcm_dais,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ARRAY_SIZE(mt2701_afe_pcm_dais));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) dev_warn(dev, "err_dai_component\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) goto err_platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) err_platform:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static int mt2701_afe_pcm_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) mt2701_afe_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static const struct mt2701_soc_variants mt2701_soc_v1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .i2s_num = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static const struct mt2701_soc_variants mt2701_soc_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .has_one_heart_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .i2s_num = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static const struct of_device_id mt2701_afe_pcm_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) { .compatible = "mediatek,mt2701-audio", .data = &mt2701_soc_v1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) { .compatible = "mediatek,mt7622-audio", .data = &mt2701_soc_v2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) MODULE_DEVICE_TABLE(of, mt2701_afe_pcm_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static const struct dev_pm_ops mt2701_afe_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) mt2701_afe_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static struct platform_driver mt2701_afe_pcm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .name = "mt2701-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .of_match_table = mt2701_afe_pcm_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .pm = &mt2701_afe_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .probe = mt2701_afe_pcm_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .remove = mt2701_afe_pcm_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) module_platform_driver(mt2701_afe_pcm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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