^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mt2701-afe-common.h -- Mediatek 2701 audio driver definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Garlic Tseng <garlic.tseng@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _MT_2701_AFE_COMMON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _MT_2701_AFE_COMMON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "mt2701-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../common/mtk-base-afe.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT2701_PLL_DOMAIN_0_RATE 98304000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MT2701_PLL_DOMAIN_1_RATE 90316800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MT2701_MEMIF_DL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MT2701_MEMIF_DL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MT2701_MEMIF_DL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MT2701_MEMIF_DL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MT2701_MEMIF_DL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MT2701_MEMIF_DL_SINGLE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MT2701_MEMIF_UL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MT2701_MEMIF_UL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MT2701_MEMIF_UL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MT2701_MEMIF_UL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MT2701_MEMIF_UL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MT2701_MEMIF_DLBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MT2701_MEMIF_ULBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MT2701_MEMIF_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MT2701_IO_I2S = MT2701_MEMIF_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MT2701_IO_2ND_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MT2701_IO_3RD_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MT2701_IO_4TH_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MT2701_IO_5TH_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MT2701_IO_6TH_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MT2701_IO_MRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MT2701_IRQ_ASYS_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MT2701_IRQ_ASYS_IRQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MT2701_IRQ_ASYS_IRQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MT2701_IRQ_ASYS_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum audio_base_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MT2701_INFRA_SYS_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MT2701_TOP_AUD_MCLK_SRC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MT2701_TOP_AUD_MCLK_SRC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MT2701_TOP_AUD_A1SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MT2701_TOP_AUD_A2SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MT2701_AUDSYS_AFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MT2701_AUDSYS_AFE_CONN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MT2701_AUDSYS_A1SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MT2701_AUDSYS_A2SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MT2701_BASE_CLK_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct mt2701_i2s_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int i2s_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int i2s_asrc_fs_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int i2s_asrc_fs_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct mt2701_i2s_path {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int mclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int on[MTK_STREAM_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int occupied[MTK_STREAM_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const struct mt2701_i2s_data *i2s_data[MTK_STREAM_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk *hop_ck[MTK_STREAM_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct clk *sel_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk *div_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk *mclk_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk *asrco_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct mt2701_soc_variants {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bool has_one_heart_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int i2s_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mt2701_afe_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mt2701_i2s_path *i2s_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk *base_ck[MT2701_BASE_CLK_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk *mrgif_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bool mrg_enable[MTK_STREAM_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const struct mt2701_soc_variants *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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