Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * mt2701-afe-clock-ctrl.c  --  Mediatek 2701 afe clock ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Garlic Tseng <garlic.tseng@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	   Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "mt2701-afe-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "mt2701-afe-clock-ctrl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) static const char *const base_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	[MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	[MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	[MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	[MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	[MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	[MT2701_AUDSYS_AFE] = "audio_afe_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	[MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	[MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	[MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) int mt2701_init_clock(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		if (IS_ERR(afe_priv->base_ck[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			return PTR_ERR(afe_priv->base_ck[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	/* Get I2S related clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	for (i = 0; i < afe_priv->soc->i2s_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		struct clk *i2s_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		char name[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		snprintf(name, sizeof(name), "i2s%d_src_sel", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		i2s_path->sel_ck = devm_clk_get(afe->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		if (IS_ERR(i2s_path->sel_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			dev_err(afe->dev, "failed to get %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			return PTR_ERR(i2s_path->sel_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		snprintf(name, sizeof(name), "i2s%d_src_div", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		i2s_path->div_ck = devm_clk_get(afe->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		if (IS_ERR(i2s_path->div_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			dev_err(afe->dev, "failed to get %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			return PTR_ERR(i2s_path->div_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		if (IS_ERR(i2s_path->mclk_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			dev_err(afe->dev, "failed to get %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			return PTR_ERR(i2s_path->mclk_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		i2s_ck = devm_clk_get(afe->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		if (IS_ERR(i2s_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			dev_err(afe->dev, "failed to get %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			return PTR_ERR(i2s_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		i2s_path->hop_ck[SNDRV_PCM_STREAM_PLAYBACK] = i2s_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		i2s_ck = devm_clk_get(afe->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		if (IS_ERR(i2s_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			dev_err(afe->dev, "failed to get %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			return PTR_ERR(i2s_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		i2s_path->hop_ck[SNDRV_PCM_STREAM_CAPTURE] = i2s_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		snprintf(name, sizeof(name), "asrc%d_out_ck", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		if (IS_ERR(i2s_path->asrco_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			dev_err(afe->dev, "failed to get %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			return PTR_ERR(i2s_path->asrco_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* Some platforms may support BT path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (IS_ERR(afe_priv->mrgif_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		afe_priv->mrgif_ck = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int mt2701_afe_enable_i2s(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			  struct mt2701_i2s_path *i2s_path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			  int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ret = clk_prepare_enable(i2s_path->asrco_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		goto err_hop_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) err_hop_ck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	clk_disable_unprepare(i2s_path->asrco_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void mt2701_afe_disable_i2s(struct mtk_base_afe *afe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			    struct mt2701_i2s_path *i2s_path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			    int dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	clk_disable_unprepare(i2s_path->hop_ck[dir]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	clk_disable_unprepare(i2s_path->asrco_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return clk_prepare_enable(i2s_path->mclk_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	clk_disable_unprepare(i2s_path->mclk_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return clk_prepare_enable(afe_priv->mrgif_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	clk_disable_unprepare(afe_priv->mrgif_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Enable infra clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Enable top a1sys clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		goto err_a1sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Enable top a2sys clock gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		goto err_a2sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* Internal clock gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		goto err_afe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		goto err_audio_a1sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		goto err_audio_a2sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		goto err_afe_conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) err_afe_conn:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) err_audio_a2sys:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) err_audio_a1sys:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) err_afe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) err_a2sys:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) err_a1sys:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* Enable audio system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret = mt2701_afe_enable_audsys(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		dev_err(afe->dev, "failed to enable audio system %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	regmap_update_bits(afe->regmap, ASYS_TOP_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			   ASYS_TOP_CON_ASYS_TIMING_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			   ASYS_TOP_CON_ASYS_TIMING_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	regmap_update_bits(afe->regmap, AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			   AFE_DAC_CON0_AFE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			   AFE_DAC_CON0_AFE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Configure ASRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	regmap_update_bits(afe->regmap, ASYS_TOP_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			   ASYS_TOP_CON_ASYS_TIMING_ON, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	regmap_update_bits(afe->regmap, AFE_DAC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			   AFE_DAC_CON0_AFE_ON, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	mt2701_afe_disable_audsys(afe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int mt2701_mclk_configuration(struct mtk_base_afe *afe, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct mt2701_afe_private *priv = afe->platform_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* Set mclk source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!(MT2701_PLL_DOMAIN_0_RATE % i2s_path->mclk_rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		ret = clk_set_parent(i2s_path->sel_ck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				     priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	else if (!(MT2701_PLL_DOMAIN_1_RATE % i2s_path->mclk_rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ret = clk_set_parent(i2s_path->sel_ck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				     priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		dev_err(afe->dev, "failed to set mclk source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* Set mclk divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ret = clk_set_rate(i2s_path->div_ck, i2s_path->mclk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }