^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * skl.c - Implementation of ASoC Intel SKL HD Audio driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2015 Intel Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jeeja KP <jeeja.kp@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Derived mostly from Intel HDA driver with following copyrights:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * PeiSen Hou <pshou@realtek.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/soc-acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/soc-acpi-intel-match.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/hda_register.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/hdaudio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/hda_i915.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/hda_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <sound/intel-nhlt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <sound/intel-dsp-config.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "skl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "skl-sst-dsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "skl-sst-ipc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "../../../soc/codecs/hdac_hda.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int skl_pci_binding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) module_param_named(pci_binding, skl_pci_binding, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * initialize the PCI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned char mask, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) pci_read_config_byte(pci, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) data |= (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pci_write_config_byte(pci, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void skl_init_pci(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * TCSEL == Traffic Class Select Register, which sets PCI express QOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Ensuring these bits are 0 clears playback static on some HD Audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * The PCI register TCSEL is defined in the Intel manuals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_dbg(bus->dev, "Clearing TCSEL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void update_pci_dword(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pci_read_config_dword(pci, reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) data |= (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pci_write_config_dword(pci, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @dev: device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @enable: enable/disable flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void skl_enable_miscbdcge(struct device *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * skl_clock_power_gating: Enable/Disable clock and power gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @dev: Device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @enable: Enable/Disable flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void skl_clock_power_gating(struct device *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct hdac_bus *bus = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Update PDCGE bit of CGCTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val = enable ? AZX_CGCTL_ADSPDCGE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Update L1SEN bit of EM2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = enable ? AZX_REG_VS_EM2_L1SEN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Update ADSPPGD bit of PGCTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val = enable ? 0 : AZX_PGCTL_ADSPPGD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * While performing reset, controller may not come back properly causing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * (init chip) and then again set CGCTL.MISCBDCGE to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct hdac_ext_link *hlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) snd_hdac_set_codec_wakeup(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) skl_enable_miscbdcge(bus->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = snd_hdac_bus_init_chip(bus, full_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Reset stream-to-link mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) list_for_each_entry(hlink, &bus->hlink_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) skl_enable_miscbdcge(bus->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) snd_hdac_set_codec_wakeup(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void skl_update_d0i3c(struct device *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct hdac_bus *bus = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int timeout = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) reg = snd_hdac_chip_readb(bus, VS_D0I3C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Do not write to D0I3C until command in progress bit is cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) reg = snd_hdac_chip_readb(bus, VS_D0I3C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Highly unlikely. But if it happens, flag error explicitly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) reg = reg | AZX_REG_VS_D0I3C_I3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg = reg & (~AZX_REG_VS_D0I3C_I3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) snd_hdac_chip_writeb(bus, VS_D0I3C, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) timeout = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Wait for cmd in progress to be cleared before exiting the function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) reg = snd_hdac_chip_readb(bus, VS_D0I3C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg = snd_hdac_chip_readb(bus, VS_D0I3C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Highly unlikely. But if it happens, flag error explicitly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_dbg(bus->dev, "D0I3C register = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) snd_hdac_chip_readb(bus, VS_D0I3C));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * skl_dum_set - set DUM bit in EM2 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @bus: HD-audio core bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Addresses incorrect position reporting for capture streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Used on device power up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void skl_dum_set(struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* For the DUM bit to be set, CRST needs to be out of reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) skl_enable_miscbdcge(bus->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) snd_hdac_bus_exit_link_reset(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) skl_enable_miscbdcge(bus->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* called from IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) snd_pcm_period_elapsed(hstr->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static irqreturn_t skl_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct hdac_bus *bus = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!pm_runtime_active(bus->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) spin_lock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) status = snd_hdac_chip_readl(bus, INTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (status == 0 || status == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) spin_unlock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* clear rirb int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) status = snd_hdac_chip_readb(bus, RIRBSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (status & RIRB_INT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (status & RIRB_INT_RESPONSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) snd_hdac_bus_update_rirb(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) spin_unlock(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct hdac_bus *bus = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) status = snd_hdac_chip_readl(bus, INTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) skl_threaded_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) KBUILD_MODNAME, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "unable to grab IRQ %d, disabling device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) skl->pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bus->irq = skl->pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pci_intx(skl->pci, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int skl_suspend_late(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct hdac_bus *bus = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return skl_suspend_late_dsp(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int _skl_suspend(struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct pci_dev *pci = to_pci_dev(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) snd_hdac_ext_bus_link_power_down_all(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = skl_suspend_dsp(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) snd_hdac_bus_stop_chip(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) update_pci_dword(pci, AZX_PCIREG_PGCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) skl_enable_miscbdcge(bus->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) snd_hdac_bus_enter_link_reset(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) skl_enable_miscbdcge(bus->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) skl_cleanup_resources(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int _skl_resume(struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) skl_init_pci(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) skl_dum_set(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) skl_init_chip(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return skl_resume_dsp(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int skl_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct hdac_bus *bus = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Do not suspend if streams which are marked ignore suspend are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * running, we need to save the state for these and continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (skl->supend_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* turn off the links and stop the CORB/RIRB DMA if it is On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) snd_hdac_ext_bus_link_power_down_all(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (bus->cmd_dma_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) snd_hdac_bus_stop_cmd_io(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) enable_irq_wake(bus->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pci_save_state(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = _skl_suspend(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) skl->fw_loaded = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int skl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct hdac_bus *bus = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct hdac_ext_link *hlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * resume only when we are not in suspend active, otherwise need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * restore the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (skl->supend_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pci_restore_state(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) snd_hdac_ext_bus_link_power_up_all(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) disable_irq_wake(bus->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * turn On the links which are On before active suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * and start the CORB/RIRB DMA if On before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * active suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) list_for_each_entry(hlink, &bus->hlink_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (hlink->ref_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) snd_hdac_ext_bus_link_power_up(hlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (bus->cmd_dma_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) snd_hdac_bus_init_cmd_io(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = _skl_resume(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* turn off the links which are off before suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) list_for_each_entry(hlink, &bus->hlink_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!hlink->ref_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) snd_hdac_ext_bus_link_power_down(hlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!bus->cmd_dma_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) snd_hdac_bus_stop_cmd_io(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int skl_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct hdac_bus *bus = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_dbg(bus->dev, "in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return _skl_suspend(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int skl_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct pci_dev *pci = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct hdac_bus *bus = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_dbg(bus->dev, "in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return _skl_resume(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct dev_pm_ops skl_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .suspend_late = skl_suspend_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * destructor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int skl_free(struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) skl->init_done = 0; /* to be sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) snd_hdac_ext_stop_streams(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (bus->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) free_irq(bus->irq, (void *)bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) snd_hdac_bus_free_stream_pages(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) snd_hdac_stream_free_all(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) snd_hdac_link_free_all(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (bus->remap_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) iounmap(bus->remap_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pci_release_regions(skl->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pci_disable_device(skl->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) snd_hdac_ext_bus_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) snd_hdac_i915_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * For each ssp there are 3 clocks (mclk/sclk/sclkfs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * e.g. for ssp0, clocks will be named as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * So for skl+, there are 6 ssps, so 18 clocks will be created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct skl_ssp_clk skl_ssp_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {.name = "ssp2_sclkfs"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {.name = "ssp5_sclkfs"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl_dev *skl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct snd_soc_acpi_mach *machines)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct snd_soc_acpi_mach *mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* point to common table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mach = snd_soc_acpi_intel_hda_machines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* all entries in the machine table use the same firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mach->fw_filename = machines->fw_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int skl_find_machine(struct skl_dev *skl, void *driver_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct snd_soc_acpi_mach *mach = driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct skl_machine_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mach = snd_soc_acpi_find_machine(mach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!mach) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_dbg(bus->dev, "No matching I2S machine driver found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mach = skl_find_hda_machine(skl, driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (!mach) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(bus->dev, "No matching machine driver found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) skl->mach = mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) skl->fw_name = mach->fw_filename;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pdata = mach->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) skl->use_tplg_pcm = pdata->use_tplg_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mach->mach_params.dmic_num =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) intel_nhlt_get_dmic_geo(&skl->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) skl->nhlt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int skl_machine_device_register(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct snd_soc_acpi_mach *mach = skl->mach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pdev = platform_device_alloc(mach->drv_name, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (pdev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_err(bus->dev, "platform device alloc failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mach->mach_params.platform = dev_name(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mach->mach_params.codec_mask = bus->codec_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(bus->dev, "failed to add machine device platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(bus->dev, "failed to add machine device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) skl->i2s_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static void skl_machine_device_unregister(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (skl->i2s_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) platform_device_unregister(skl->i2s_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int skl_dmic_device_register(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* SKL has one dmic port, so allocate dmic device for this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pdev = platform_device_alloc("dmic-codec", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(bus->dev, "failed to allocate dmic device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) skl->dmic_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static void skl_dmic_device_unregister(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (skl->dmic_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) platform_device_unregister(skl->dmic_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static struct skl_clk_parent_src skl_clk_src[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { .clk_id = SKL_XTAL, .name = "xtal" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (skl_clk_src[i].clk_id == clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return &skl_clk_src[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static void init_skl_xtal_rate(int pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) switch (pci_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case 0x9d70:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case 0x9d71:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) skl_clk_src[0].rate = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) skl_clk_src[0].rate = 19200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int skl_clock_device_register(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct platform_device_info pdevinfo = {NULL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct skl_clk_pdata *clk_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (!skl->nhlt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!clk_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) init_skl_xtal_rate(skl->pci->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) clk_pdata->parent_clks = skl_clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) clk_pdata->ssp_clks = skl_ssp_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Query NHLT to fill the rates and parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) skl_get_clks(skl, clk_pdata->ssp_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) clk_pdata->pvt_data = skl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Register Platform device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) pdevinfo.parent = &skl->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pdevinfo.id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) pdevinfo.name = "skl-ssp-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pdevinfo.data = clk_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pdevinfo.size_data = sizeof(*clk_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) skl->clk_dev = platform_device_register_full(&pdevinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return PTR_ERR_OR_ZERO(skl->clk_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static void skl_clock_device_unregister(struct skl_dev *skl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (skl->clk_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) platform_device_unregister(skl->clk_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define IDISP_INTEL_VENDOR_ID 0x80860000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * load the legacy codec driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static void load_codec_module(struct hda_codec *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) char modalias[MODULE_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) const char *mod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mod = modalias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_dbg(&codec->core.dev, "loading %s codec module\n", mod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) request_module(mod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Probe the given codec address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int probe_codec(struct hdac_bus *bus, int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned int res = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct hdac_hda_priv *hda_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct hdac_device *hdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mutex_lock(&bus->cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) snd_hdac_bus_send_cmd(bus, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) snd_hdac_bus_get_response(bus, addr, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mutex_unlock(&bus->cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (res == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!hda_codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) hda_codec->codec.bus = skl_to_hbus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) hdev = &hda_codec->codec.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) err = snd_hdac_ext_bus_device_init(bus, addr, hdev, HDA_DEV_ASOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* use legacy bus only for HDA codecs, idisp uses ext bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) hdev->type = HDA_DEV_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) load_codec_module(&hda_codec->codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (!hdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return snd_hdac_ext_bus_device_init(bus, addr, hdev, HDA_DEV_ASOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Codec initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void skl_codec_create(struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int c, max_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) max_slots = HDA_MAX_CODECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* First try to probe all given codec slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) for (c = 0; c < max_slots; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if ((bus->codec_mask & (1 << c))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (probe_codec(bus, c) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * Some BIOSen give you wrong codec addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * that don't exist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_warn(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "Codec #%d probe error; disabling it...\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) bus->codec_mask &= ~(1 << c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * More badly, accessing to a non-existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * codec often screws up the controller bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * and disturbs the further communications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * Thus if an error occurs during probing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * better to reset the controller bus to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * back to the sanity state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) snd_hdac_bus_stop_chip(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) skl_init_chip(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int skl_i915_init(struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * The HDMI codec is in GPU so we need to ensure that it is powered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * up and ready for probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) err = snd_hdac_i915_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static void skl_probe_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct skl_dev *skl = container_of(work, struct skl_dev, probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct hdac_bus *bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct hdac_ext_link *hlink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) err = skl_i915_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) skl_init_pci(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) skl_dum_set(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) err = skl_init_chip(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_err(bus->dev, "Init chip failed with err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* codec detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (!bus->codec_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_info(bus->dev, "no hda codecs found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* create codec instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) skl_codec_create(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* register platform dai and controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) err = skl_platform_register(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_err(bus->dev, "platform register failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) err = skl_machine_device_register(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_err(bus->dev, "machine register failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * we are done probing so decrement link counts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) list_for_each_entry(hlink, &bus->hlink_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) snd_hdac_ext_bus_link_put(bus, hlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* configure PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) pm_runtime_put_noidle(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) pm_runtime_allow(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) skl->init_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * constructor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int skl_create(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct skl_dev **rskl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct hdac_ext_bus_ops *ext_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct skl_dev *skl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct hdac_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct hda_bus *hbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) *rskl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!skl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) hbus = skl_to_hbus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) INIT_LIST_HEAD(&skl->ppl_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) INIT_LIST_HEAD(&skl->bind_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ext_ops = snd_soc_hdac_hda_get_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) snd_hdac_ext_bus_init(bus, &pci->dev, NULL, ext_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) bus->use_posbuf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) skl->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) INIT_WORK(&skl->probe_work, skl_probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) bus->bdl_pos_adj = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) mutex_init(&hbus->prepare_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) hbus->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) hbus->mixer_assigned = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) hbus->modelname = "sklbus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) *rskl = skl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static int skl_first_init(struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct pci_dev *pci = skl->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) unsigned short gcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int cp_streams, pb_streams, start_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) err = pci_request_regions(pci, "Skylake HD audio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) bus->addr = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) bus->remap_addr = pci_ioremap_bar(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (bus->remap_addr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_err(bus->dev, "ioremap error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) snd_hdac_bus_parse_capabilities(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* check if PPCAP exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (!bus->ppcap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev_err(bus->dev, "bus ppcap not set, HDAudio or DSP not present?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (skl_acquire_irq(bus, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) synchronize_irq(bus->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) gcap = snd_hdac_chip_readw(bus, GCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* read number of streams from GCAP register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) cp_streams = (gcap >> 8) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) pb_streams = (gcap >> 12) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (!pb_streams && !cp_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dev_err(bus->dev, "no streams found in GCAP definitions?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) bus->num_streams = cp_streams + pb_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* allow 64bit DMA address if supported by H/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dma_set_mask(bus->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* initialize streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) snd_hdac_ext_stream_init_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) start_idx = cp_streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) snd_hdac_ext_stream_init_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) err = snd_hdac_bus_alloc_stream_pages(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static int skl_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct skl_dev *skl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct hdac_bus *bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) switch (skl_pci_binding) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) case SND_SKL_PCI_BIND_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) err = snd_intel_dsp_driver_probe(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (err != SND_INTEL_DSP_DRIVER_ANY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) err != SND_INTEL_DSP_DRIVER_SST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) case SND_SKL_PCI_BIND_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dev_info(&pci->dev, "Module parameter forced binding with HDAudio legacy, aborting probe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) case SND_SKL_PCI_BIND_ASOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* we use ext core ops, so provide NULL for ops here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) err = skl_create(pci, &skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) bus = skl_to_bus(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) err = skl_first_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_err(bus->dev, "skl_first_init failed with err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) skl->pci_id = pci->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) device_disable_async_suspend(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) skl->nhlt = intel_nhlt_init(bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (skl->nhlt == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dev_err(bus->dev, "no nhlt info found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDAudio codec\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) err = skl_nhlt_create_sysfs(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) goto out_nhlt_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) skl_nhlt_update_topology_bin(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* create device for dsp clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) err = skl_clock_device_register(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) goto out_clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) pci_set_drvdata(skl->pci, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) err = skl_find_machine(skl, (void *)pci_id->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto out_nhlt_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) err = skl_init_dsp(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_dbg(bus->dev, "error failed to register dsp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) goto out_nhlt_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) skl->enable_miscbdcge = skl_enable_miscbdcge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) skl->clock_power_gating = skl_clock_power_gating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (bus->mlcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) snd_hdac_ext_bus_get_ml_capabilities(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* create device for soc dmic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) err = skl_dmic_device_register(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) goto out_dsp_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) schedule_work(&skl->probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) out_dsp_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) skl_free_dsp(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) out_clk_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) skl_clock_device_unregister(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) out_nhlt_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (skl->nhlt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) intel_nhlt_free(skl->nhlt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) skl_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static void skl_shutdown(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct hdac_bus *bus = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct hdac_ext_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct skl_dev *skl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (!skl->init_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) snd_hdac_ext_stop_streams(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) list_for_each_entry(s, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) stream = stream_to_hdac_ext_stream(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) snd_hdac_ext_stream_decouple(bus, stream, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) snd_hdac_bus_stop_chip(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static void skl_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct hdac_bus *bus = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct skl_dev *skl = bus_to_skl(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) cancel_work_sync(&skl->probe_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pm_runtime_get_noresume(&pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* codec removal, invoke bus_device_remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) snd_hdac_ext_bus_device_remove(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) skl_platform_unregister(&pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) skl_free_dsp(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) skl_machine_device_unregister(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) skl_dmic_device_unregister(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) skl_clock_device_unregister(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) skl_nhlt_remove_sysfs(skl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (skl->nhlt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) intel_nhlt_free(skl->nhlt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) skl_free(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) dev_set_drvdata(&pci->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* PCI IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static const struct pci_device_id skl_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* Sunrise Point-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) { PCI_DEVICE(0x8086, 0x9d70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* BXT-P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) { PCI_DEVICE(0x8086, 0x5a98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* KBL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) { PCI_DEVICE(0x8086, 0x9D71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* GLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) { PCI_DEVICE(0x8086, 0x3198),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* CNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) { PCI_DEVICE(0x8086, 0x9dc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* CFL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) { PCI_DEVICE(0x8086, 0xa348),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* CML-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) { PCI_DEVICE(0x8086, 0x02c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* CML-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) { PCI_DEVICE(0x8086, 0x06c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) MODULE_DEVICE_TABLE(pci, skl_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* pci_driver definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static struct pci_driver skl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .id_table = skl_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .probe = skl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .remove = skl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .shutdown = skl_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .pm = &skl_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) module_pci_driver(skl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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